X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fclk%2Frockchip%2Fclk_rk322x.c;h=ff52b5522903ea026c779cbc93e4faf9e1234366;hb=bb7ab1ccfec9aa4e2df3e8eb49ca85f6c0c65560;hp=d7f6a3c313e6c86143dc3931fc00196981d8b534;hpb=390194d43fa4478ddb638164ddb114c979f3e57a;p=oweals%2Fu-boot.git diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index d7f6a3c313..ff52b55229 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -117,16 +117,16 @@ static void rkclk_init(struct rk322x_cru *cru) pclk_div << CORE_PERI_DIV_SHIFT); /* - * select apll as pd_bus bus clock source and + * select gpll as pd_bus bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); - pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); - hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], @@ -385,11 +385,22 @@ static int rk322x_clk_probe(struct udevice *dev) static int rk322x_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev); - if (ret) - debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk322x_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk322x_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } return 0; }