X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fclk%2Fclk_zynqmp.c;h=167f3f75a19cf6a593a97093e358a151bc83ef21;hb=8eee1d3ec6776d84e8b45d346e73734456518017;hp=4ef8662af56035720a22f92d9460cff52bd7e370;hpb=89a650e0ffb89faaea1b9e6ad8cf2b38203435f2;p=oweals%2Fu-boot.git

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 4ef8662af5..167f3f75a1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * ZynqMP clock driver
  *
  * Copyright (C) 2016 Xilinx, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
@@ -13,8 +12,6 @@
 #include <asm/arch/sys_proto.h>
 #include <dm.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
 
@@ -106,6 +103,8 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
 #define PLLCTRL_BYPASS_SHFT	3
 #define PLLCTRL_POST_SRC_SHFT	24
 #define PLLCTRL_POST_SRC_MASK	(0x7 << PLLCTRL_POST_SRC_SHFT)
+#define PLLCTRL_PRE_SRC_SHFT	20
+#define PLLCTRL_PRE_SRC_MASK	(0x7 << PLLCTRL_PRE_SRC_SHFT)
 
 
 #define NUM_MIO_PINS	77
@@ -313,8 +312,8 @@ static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 	u32 src_sel;
 
 	if (is_pre_src)
-		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
-			   PLLCTRL_POST_SRC_SHFT;
+		src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
+			   PLLCTRL_PRE_SRC_SHFT;
 	else
 		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 			   PLLCTRL_POST_SRC_SHFT;
@@ -702,6 +701,7 @@ static struct clk_ops zynqmp_clk_ops = {
 };
 
 static const struct udevice_id zynqmp_clk_ids[] = {
+	{ .compatible = "xlnx,zynqmp-clk" },
 	{ .compatible = "xlnx,zynqmp-clkc" },
 	{ }
 };