X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fblock%2Fahci.c;h=0d19dd25a3441c95d1e159dfeacacdd4a2960cc3;hb=6bed24cc62ecd8d7a96c34cf1cf3e5e093f7be62;hp=cab7f8c7ad9f44a609fcf909e38af0a7b4777d1d;hpb=345be0b26734c560e8b33531ab21a1272179c5c3;p=oweals%2Fu-boot.git diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index cab7f8c7ad..0d19dd25a3 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -3,26 +3,9 @@ * Author: Jason Jin * Zhang Wei * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ * * with the reference on libata and ahci drvier in kernel - * */ #include @@ -33,14 +16,14 @@ #include #include #include -#include +#include #include #include static int ata_io_flush(u8 port); struct ahci_probe_ent *probe_ent = NULL; -hd_driveid_t *ataid[AHCI_MAX_PORTS]; +u16 *ataid[AHCI_MAX_PORTS]; #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) @@ -55,18 +38,18 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #endif /* Maximum timeouts for each event */ -#define WAIT_MS_SPINUP 10000 -#define WAIT_MS_DATAIO 5000 +#define WAIT_MS_SPINUP 20000 +#define WAIT_MS_DATAIO 10000 #define WAIT_MS_FLUSH 5000 -#define WAIT_MS_LINKUP 4 +#define WAIT_MS_LINKUP 200 -static inline u32 ahci_port_base(u32 base, u32 port) +static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); } -static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, +static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, unsigned int port_idx) { base = ahci_port_base(base, port_idx); @@ -78,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, #define msleep(a) udelay(a * 1000) -static void ahci_dcache_flush_range(unsigned begin, unsigned len) +static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -92,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned len) * controller is invalidated from dcache; next access comes from * physical RAM. */ -static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) +static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -111,7 +94,7 @@ static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) AHCI_PORT_PRIV_DMA_SZ); } -static int waiting_for_cmd_completed(volatile u8 *offset, +static int waiting_for_cmd_completed(void __iomem *offset, int timeout_msec, u32 sign) { @@ -124,6 +107,62 @@ static int waiting_for_cmd_completed(volatile u8 *offset, return (i < timeout_msec) ? 0 : -1; } +int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) +{ + u32 tmp; + int j = 0; + void __iomem *port_mmio = probe_ent->port[port].port_mmio; + + /* + * Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + return 0; + udelay(1000); + j++; + } + return 1; +} + +#ifdef CONFIG_SUNXI_AHCI +/* The sunxi AHCI controller requires this undocumented setup */ +static void sunxi_dma_init(void __iomem *port_mmio) +{ + clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); +} +#endif + +int ahci_reset(void __iomem *base) +{ + int i = 1000; + u32 __iomem *host_ctl_reg = base + HOST_CTL; + u32 tmp = readl(host_ctl_reg); /* global controller reset */ + + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, host_ctl_reg); + + /* + * reset must complete within 1 second, or + * the hardware should be considered fried. + */ + do { + udelay(1000); + tmp = readl(host_ctl_reg); + i--; + } while ((i > 0) && (tmp & HOST_RESET)); + + if (i == 0) { + printf("controller reset failed (0x%x)\n", tmp); + return -1; + } + + return 0; +} static int ahci_host_init(struct ahci_probe_ent *probe_ent) { @@ -132,10 +171,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) u16 tmp16; unsigned short vendor; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 tmp, cap_save, cmd; - int i, j; - volatile u8 *port_mmio; + int i, j, ret; + void __iomem *port_mmio; + u32 port_map; debug("ahci_host_init: start\n"); @@ -143,23 +183,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ - /* global controller reset */ - tmp = readl(mmio + HOST_CTL); - if ((tmp & HOST_RESET) == 0) - writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); - - /* reset must complete within 1 second, or - * the hardware should be considered fried. - */ - i = 1000; - do { - udelay(1000); - tmp = readl(mmio + HOST_CTL); - if (!i--) { - debug("controller reset failed (0x%x)\n", tmp); - return -1; - } - } while (tmp & HOST_RESET); + ret = ahci_reset(probe_ent->mmio_base); + if (ret) + return ret; writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); writel(cap_save, mmio + HOST_CAP); @@ -177,6 +203,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) #endif probe_ent->cap = readl(mmio + HOST_CAP); probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + port_map = probe_ent->port_map; probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; debug("cap 0x%x port_map 0x%x n_ports %d\n", @@ -186,9 +213,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; for (i = 0; i < probe_ent->n_ports; i++) { - probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + if (!(port_map & (1 << i))) + continue; + probe_ent->port[i].port_mmio = ahci_port_base(mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + ahci_setup_port(&probe_ent->port[i], mmio, i); /* make sure port is not active */ tmp = readl(port_mmio + PORT_CMD); @@ -205,27 +234,20 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); } +#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + /* Add the spinup command to whatever mode bits may * already be on in the command register. */ cmd = readl(port_mmio + PORT_CMD); - cmd |= PORT_CMD_FIS_RX; cmd |= PORT_CMD_SPIN_UP; writel_with_flush(cmd, port_mmio + PORT_CMD); - /* Bring up SATA link. - * SATA link bringup time is usually less than 1 ms; only very - * rarely has it taken between 1-2 ms. Never seen it above 2 ms. - */ - j = 0; - while (j < WAIT_MS_LINKUP) { - tmp = readl(port_mmio + PORT_SCR_STAT); - if ((tmp & 0xf) == 0x3) - break; - udelay(1000); - j++; - } - if (j == WAIT_MS_LINKUP) { + /* Bring up SATA link. */ + ret = ahci_link_up(probe_ent, i); + if (ret) { printf("SATA link %d timeout.\n", i); continue; } else { @@ -242,11 +264,23 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) j = 0; while (j < WAIT_MS_SPINUP) { tmp = readl(port_mmio + PORT_TFDATA); - if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ))) + if (!(tmp & (ATA_BUSY | ATA_DRQ))) break; udelay(1000); + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + break; j++; } + + tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_COMINIT) { + debug("SATA link %d down (COMINIT received), retrying...\n", i); + i--; + continue; + } + printf("Target spinup took %d ms.\n", j); if (j == WAIT_MS_SPINUP) debug("timeout.\n"); @@ -265,13 +299,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(1 << i, mmio + HOST_IRQ_STAT); - /* set irq mask (enables interrupts) */ - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("SATA port %d status: 0x%x\n", i, tmp); - if ((tmp & 0xf) == 0x03) + if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) probe_ent->link_port_map |= (0x01 << i); } @@ -295,7 +326,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) pci_dev_t pdev = probe_ent->dev; u16 cc; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 vers, cap, cap2, impl, speed; const char *speed_s; const char *scc_s; @@ -368,9 +399,12 @@ static int ahci_init_one(pci_dev_t pdev) u16 vendor; int rc; - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; @@ -382,8 +416,9 @@ static int ahci_init_one(pci_dev_t pdev) probe_ent->pio_mask = 0x1f; probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); - debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); + probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5, + PCI_REGION_MEM); + debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base); /* Take from kernel: * JMicron-specific fixup: @@ -424,7 +459,7 @@ static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) for (i = 0; i < sg_count; i++) { ahci_sg->addr = - cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < MAX_DATA_BYTE_COUNT @@ -442,8 +477,11 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - pp->cmd_slot->tbl_addr_hi = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); +#ifdef CONFIG_PHYS_64BIT + pp->cmd_slot->tbl_addr_hi = + cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); +#endif } @@ -451,7 +489,7 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) static void ahci_set_feature(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; @@ -459,7 +497,7 @@ static void ahci_set_feature(u8 port) memset(fis, 0, sizeof(fis)); fis[0] = 0x27; fis[1] = 1 << 7; - fis[2] = ATA_CMD_SETF; + fis[2] = ATA_CMD_SET_FEATURES; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; @@ -476,13 +514,27 @@ static void ahci_set_feature(u8 port) } #endif +static int wait_spinup(void __iomem *port_mmio) +{ + ulong start; + u32 tf_data; + + start = get_timer(0); + do { + tf_data = readl(port_mmio + PORT_TFDATA); + if (!(tf_data & ATA_BUSY)) + return 0; + } while (get_timer(start) < WAIT_MS_SPINUP); + + return -ETIMEDOUT; +} static int ahci_port_start(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 port_status; - u32 mem; + void __iomem *mem; debug("Enter start port: %d\n", port); port_status = readl(port_mmio + PORT_SCR_STAT); @@ -492,15 +544,16 @@ static int ahci_port_start(u8 port) return -1; } - mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); - printf("No mem for table!\n"); + printf("%s: No mem for table!\n", __func__); return -ENOMEM; } - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ - memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* Aligned to 2048-bytes */ + mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); + memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, @@ -508,7 +561,7 @@ static int ahci_port_start(u8 port) */ pp->cmd_slot = (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); - debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); + debug("cmd_slot = %p\n", pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); /* @@ -522,23 +575,32 @@ static int ahci_port_start(u8 port) * and its scatter-gather table */ pp->cmd_tbl = virt_to_phys((void *)mem); - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + writel_with_flush((unsigned long)pp->cmd_slot, + port_mmio + PORT_LST_ADDR); writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); +#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | PORT_CMD_START, port_mmio + PORT_CMD); debug("Exit start port %d\n", port); - return 0; + /* + * Make sure interface is not busy based on error and status + * information from task file data register before proceeding + */ + return wait_spinup(port_mmio); } @@ -547,7 +609,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 opts; u32 port_status; int sg_count; @@ -572,7 +634,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, ahci_fill_cmd_slot(pp, opts); ahci_dcache_flush_sata_cmd(pp); - ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -582,7 +644,8 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, return -1; } - ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_invalidate_range((unsigned long)buf, + (unsigned long)buf_len); debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); return 0; @@ -597,33 +660,12 @@ static char *ata_id_strcpy(u16 *target, u16 *src, int len) return (char *)target; } - -static void dump_ataid(hd_driveid_t *ataid) -{ - debug("(49)ataid->capability = 0x%x\n", ataid->capability); - debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); - debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); - debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); - debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); - debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); - debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); - debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); - debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); - debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); - debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); - debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); - debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); - debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); - debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); -} - - /* * SCSI INQUIRY command operation. */ static int ata_scsiop_inquiry(ccb *pccb) { - u8 hdr[] = { + static const u8 hdr[] = { 0, 0, 0x5, /* claim SPC-3 version compatibility */ @@ -631,7 +673,8 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; - u8 *tmpid; + u16 *idbuf; + ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; /* Clean ccb data buffer */ @@ -646,28 +689,37 @@ static int ata_scsiop_inquiry(ccb *pccb) /* Construct the FIS */ fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ + fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ /* Read id from sata */ port = pccb->target; - if (!(tmpid = malloc(sizeof(hd_driveid_t)))) - return -ENOMEM; - if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, - sizeof(hd_driveid_t), 0)) { + if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, + ATA_ID_WORDS * 2, 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } - if (ataid[port]) - free(ataid[port]); - ataid[port] = (hd_driveid_t *) tmpid; + if (!ataid[port]) { + ataid[port] = malloc(ATA_ID_WORDS * 2); + if (!ataid[port]) { + printf("%s: No memory for ataid[port]\n", __func__); + return -ENOMEM; + } + } + + idbuf = ataid[port]; + + memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); + ata_swap_buf_le16(idbuf, ATA_ID_WORDS); memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); - dump_ataid(ataid[port]); +#ifdef DEBUG + ata_dump_id(idbuf); +#endif return 0; } @@ -677,18 +729,25 @@ static int ata_scsiop_inquiry(ccb *pccb) */ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) { - u32 lba = 0; + lbaint_t lba = 0; u16 blocks = 0; u8 fis[20]; u8 *user_buffer = pccb->pdata; u32 user_buffer_size = pccb->datalen; /* Retrieve the base LBA number from the ccb structure. */ - memcpy(&lba, pccb->cmd + 2, sizeof(lba)); - lba = be32_to_cpu(lba); + if (pccb->cmd[0] == SCSI_READ16) { + memcpy(&lba, pccb->cmd + 2, 8); + lba = be64_to_cpu(lba); + } else { + u32 temp; + memcpy(&temp, pccb->cmd + 2, 4); + lba = be32_to_cpu(temp); + } /* - * And the number of blocks. + * Retrieve the base LBA number and the block count from + * the ccb structure. * * For 10-byte and 16-byte SCSI R/W commands, transfer * length 0 means transfer 0 block of data. @@ -697,10 +756,13 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) * * WARNING: one or two older ATA drives treat 0 as 0... */ - blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); + if (pccb->cmd[0] == SCSI_READ16) + blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); + else + blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); - debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", - is_write ? "write" : "read", (unsigned)lba, blocks); + debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", + is_write ? "write" : "read", blocks, lba); /* Preset the FIS */ memset(fis, 0, sizeof(fis)); @@ -713,22 +775,31 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) u16 now_blocks; /* number of blocks per iteration */ u32 transfer_size; /* number of bytes per iteration */ - now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); + now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); - transfer_size = ATA_BLOCKSIZE * now_blocks; + transfer_size = ATA_SECT_SIZE * now_blocks; if (transfer_size > user_buffer_size) { printf("scsi_ahci: Error: buffer too small.\n"); return -EIO; } - /* LBA48 SATA command but only use 32bit address range within - * that. The next smaller command range (28bit) is too small. + /* + * LBA48 SATA command but only use 32bit address range within + * that (unless we've enabled 64bit LBA support). The next + * smaller command range (28bit) is too small. */ fis[4] = (lba >> 0) & 0xff; fis[5] = (lba >> 8) & 0xff; fis[6] = (lba >> 16) & 0xff; fis[7] = 1 << 6; /* device reg: set LBA mode */ fis[8] = ((lba >> 24) & 0xff); +#ifdef CONFIG_SYS_64BIT_LBA + if (pccb->cmd[0] == SCSI_READ16) { + fis[9] = ((lba >> 32) & 0xff); + fis[10] = ((lba >> 40) & 0xff); + } +#endif + fis[3] = 0xe0; /* features */ /* Block (sector) count */ @@ -737,7 +808,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) /* Read/Write from ahci */ if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), - user_buffer, user_buffer_size, + user_buffer, transfer_size, is_write)) { debug("scsi_ahci: SCSI %s10 command failure.\n", is_write ? "WRITE" : "READ"); @@ -770,6 +841,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) static int ata_scsiop_read_capacity10(ccb *pccb) { u32 cap; + u64 cap64; u32 block_size; if (!ataid[pccb->target]) { @@ -779,18 +851,11 @@ static int ata_scsiop_read_capacity10(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; - if (cap48[2] || cap48[3]) { - cap = 0xffffffff; - } else { - cap = (le16_to_cpu(cap48[1]) << 16) | - (le16_to_cpu(cap48[0])); - } - } + cap64 = ata_id_n_sectors(ataid[pccb->target]); + if (cap64 > 0x100000000ULL) + cap64 = 0xffffffff; - cap = cpu_to_be32(cap); + cap = cpu_to_be32(cap64); memcpy(pccb->pdata, &cap, sizeof(cap)); block_size = cpu_to_be32((u32)512); @@ -815,12 +880,7 @@ static int ata_scsiop_read_capacity16(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); - cap = le64_to_cpu(cap); - } - + cap = ata_id_n_sectors(ataid[pccb->target]); cap = cpu_to_be64(cap); memcpy(pccb->pdata, &cap, sizeof(cap)); @@ -845,6 +905,7 @@ int scsi_exec(ccb *pccb) int ret; switch (pccb->cmd[0]) { + case SCSI_READ16: case SCSI_READ10: ret = ata_scsiop_read_write(pccb, 0); break; @@ -902,14 +963,17 @@ void scsi_low_level_init(int busdevfunc) } #ifdef CONFIG_SCSI_AHCI_PLAT -int ahci_init(u32 base) +int ahci_init(void __iomem *base) { int i, rc = 0; u32 linkmap; - memset(ataid, 0, sizeof(ataid)); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->host_flags = ATA_FLAG_SATA @@ -945,6 +1009,11 @@ int ahci_init(u32 base) err_out: return rc; } + +void __weak scsi_init(void) +{ +} + #endif /* @@ -960,7 +1029,7 @@ static int ata_io_flush(u8 port) { u8 fis[20]; struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ /* Preset the FIS */ @@ -983,12 +1052,11 @@ static int ata_io_flush(u8 port) } -void scsi_bus_reset(void) +__weak void scsi_bus_reset(void) { /*Not implement*/ } - void scsi_print_error(ccb * pccb) { /*The ahci error info can be read in the ahci driver*/