X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=doc%2Fman3%2FOPENSSL_ia32cap.pod;h=6c2d4b78ef79fd0a258e584e350577450449fa0b;hb=47ec2367ebf6082abb103e66e609feb5c128d358;hp=60dd96484c7d9702f5c6beec8d4b4eed0c0abbce;hpb=99d63d4662e16afbeff49f29b48f1c87d5558ed0;p=oweals%2Fopenssl.git

diff --git a/doc/man3/OPENSSL_ia32cap.pod b/doc/man3/OPENSSL_ia32cap.pod
index 60dd96484c..6c2d4b78ef 100644
--- a/doc/man3/OPENSSL_ia32cap.pod
+++ b/doc/man3/OPENSSL_ia32cap.pod
@@ -19,7 +19,7 @@ between different code paths to provide optimal performance across wide
 range of processors. For the moment of this writing following bits are
 significant:
 
-=over
+=over 4
 
 =item bit #4 denoting presence of Time-Stamp Counter.
 
@@ -86,7 +86,7 @@ are applied, most notably in AES assembler module.
 The capability vector is further extended with EBX value returned by
 CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
 
-=over
+=over 4
 
 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
 
@@ -101,12 +101,19 @@ and RORX;
 
 =item bit #64+19 denoting availability of ADCX and ADOX instructions;
 
+=item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
+a.k.a. AVX512IFMA extension;
+
 =item bit #64+29 denoting availability of SHA extension;
 
 =item bit #64+30 denoting availability of AVX512BW extension;
 
 =item bit #64+31 denoting availability of AVX512VL extension;
 
+=item bit #64+41 denoting availability of VAES extension;
+
+=item bit #64+42 denoting availability of VPCLMULQDQ extension;
+
 =back
 
 To control this extended capability word use ':' as delimiter when
@@ -117,7 +124,7 @@ extensions.
 It should be noted that whether or not some of the most "fancy"
 extension code paths are actually assembled depends on current assembler
 version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA extension code
-paths are always assembled. Besides that, minimum assembler version
+paths are always assembled. Apart from that, minimum assembler version
 requirements are summarized in below table:
 
    Extension   | GNU as | nasm   | llvm
@@ -125,13 +132,34 @@ requirements are summarized in below table:
    AVX         | 2.19   | 2.09   | 3.0
    AVX2        | 2.22   | 2.10   | 3.1
    ADCX/ADOX   | 2.23   | 2.10   | 3.3
-   AVX512      | 2.25   | 2.11.8 | 3.6
+   AVX512      | 2.25   | 2.11.8 | see NOTES
+   AVX512IFMA  | 2.26   | 2.11.8 | see NOTES
+   VAES        | 2.30   | 2.13.3 |
+
+=head1 NOTES
+
+Even though AVX512 support was implemented in llvm 3.6, compilation of
+assembly modules apparently requires explicit -march flag. But then
+compiler generates processor-specific code, which in turn contradicts
+the mere idea of run-time switch execution facilitated by the variable
+in question. Till the limitation is lifted, it's possible to work around
+the problem by making build procedure use following script:
+
+   #!/bin/sh
+   exec clang -no-integrated-as "$@"
+
+instead of real clang. In which case it doesn't matter which clang
+version is used, as it is GNU assembler version that will be checked.
+
+=head1 RETURN VALUES
+
+Not available.
 
 =head1 COPYRIGHT
 
-Copyright 2004-2016 The OpenSSL Project Authors. All Rights Reserved.
+Copyright 2004-2018 The OpenSSL Project Authors. All Rights Reserved.
 
-Licensed under the OpenSSL license (the "License").  You may not use
+Licensed under the Apache License 2.0 (the "License").  You may not use
 this file except in compliance with the License.  You can obtain a copy
 in the file LICENSE in the source distribution or at
 L<https://www.openssl.org/source/license.html>.