X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=crypto%2Fsparc_arch.h;h=c3843c01b8a363a41bc11e92f567620dc17fe078;hb=349e6b2b0aea737422fedfa28467bed5571ead2a;hp=f675710307f7aee435a0723509da423412d603e2;hpb=1fda639ae756eb87f585b7d5114490d4ffe649a1;p=oweals%2Fopenssl.git

diff --git a/crypto/sparc_arch.h b/crypto/sparc_arch.h
index f675710307..c3843c01b8 100644
--- a/crypto/sparc_arch.h
+++ b/crypto/sparc_arch.h
@@ -1,10 +1,6 @@
 #ifndef __SPARC_ARCH_H__
 #define __SPARC_ARCH_H__
 
-#if !__ASSEMBLER__
-extern unsigned int OPENSSL_sparcv9cap_P[];
-#endif
-
 #define SPARCV9_TICK_PRIVILEGED	(1<<0)
 #define SPARCV9_PREFER_FPU	(1<<1)
 #define SPARCV9_VIS1		(1<<2)
@@ -13,6 +9,7 @@ extern unsigned int OPENSSL_sparcv9cap_P[];
 #define SPARCV9_BLK		(1<<5)	/* VIS1 block copy */
 #define SPARCV9_VIS3		(1<<6)
 #define SPARCV9_RANDOM		(1<<7)
+#define SPARCV9_64BIT_STACK	(1<<8)
 
 /*
  * OPENSSL_sparcv9cap_P[1] is copy of Compatibility Feature Register,
@@ -32,4 +29,73 @@ extern unsigned int OPENSSL_sparcv9cap_P[];
 #define CFR_MONTSQR	0x00000400 /* Supports MONTSQR opcodes */
 #define CFR_CRC32C	0x00000800 /* Supports CRC32C opcodes  */
 
+#if defined(OPENSSL_PIC) && !defined(__PIC__)
+# define __PIC__
+#endif
+
+#if defined(__SUNPRO_C) && defined(__sparcv9) && !defined(__arch64__)
+# define __arch64__
+#endif
+
+#define SPARC_PIC_THUNK(reg)	\
+	.align	32;		\
+.Lpic_thunk:			\
+	jmp	%o7 + 8;	\
+	 add	%o7, reg, reg;
+
+#define SPARC_PIC_THUNK_CALL(reg)			\
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), reg;	\
+	call	.Lpic_thunk;				\
+	 or	reg, %lo(_GLOBAL_OFFSET_TABLE_+4), reg;
+
+#if 1
+# define SPARC_SETUP_GOT_REG(reg)	SPARC_PIC_THUNK_CALL(reg)
+#else
+# define SPARC_SETUP_GOT_REG(reg)	\
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), reg;	\
+	call	.+8;					\
+	or	reg,%lo(_GLOBAL_OFFSET_TABLE_+4), reg;	\
+	add	%o7, reg, reg
 #endif
+
+#if defined(__arch64__)
+
+# define SPARC_LOAD_ADDRESS(SYM, reg)	\
+	setx	SYM, %o7, reg;
+# define LDPTR		ldx
+# define SIZE_T_CC	%xcc
+# define STACK_FRAME	192
+# define STACK_BIAS	2047
+# define STACK_7thARG	(STACK_BIAS+176)
+
+#else
+
+# define SPARC_LOAD_ADDRESS(SYM, reg)	\
+	set	SYM, reg;
+# define LDPTR		ld
+# define SIZE_T_CC	%icc
+# define STACK_FRAME	112
+# define STACK_BIAS	0
+# define STACK_7thARG	92
+# define SPARC_LOAD_ADDRESS_LEAF(SYM,reg,tmp) SPARC_LOAD_ADDRESS(SYM,reg)
+
+#endif
+
+#ifdef __PIC__
+# undef	SPARC_LOAD_ADDRESS
+# undef SPARC_LOAD_ADDRESS_LEAF
+# define SPARC_LOAD_ADDRESS(SYM, reg)	\
+	SPARC_SETUP_GOT_REG(reg);	\
+	sethi	%hi(SYM), %o7;		\
+	or	%o7, %lo(SYM), %o7;	\
+	LDPTR	[reg + %o7], reg;
+#endif
+
+#ifndef SPARC_LOAD_ADDRESS_LEAF
+# define SPARC_LOAD_ADDRESS_LEAF(SYM, reg, tmp)	\
+	mov	%o7, tmp;			\
+	SPARC_LOAD_ADDRESS(SYM, reg)		\
+	mov	tmp, %o7;
+#endif
+
+#endif	/* __SPARC_ARCH_H__ */