X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fserial.c;h=3749811dca64a09cd203ac5bce245164a0db3b7a;hb=36b904a7fdc170a69eb94975b0e506dc2a73fa82;hp=d02ff2fa692f2585eb8a78a450c981fefc8ab732;hpb=fe8c2806cdba70479e351299881a395dc2be7785;p=oweals%2Fu-boot.git diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index d02ff2fa69..3749811dca 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -41,17 +41,26 @@ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ /*------------------------------------------------------------------------------- */ - +/* + * Travis Sawyer 15 September 2004 + * Added CONFIG_SERIAL_MULTI support + */ #include #include #include #include #include "vecnum.h" -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO #include #endif +DECLARE_GLOBAL_DATA_PTR; + /*****************************************************************************/ #ifdef CONFIG_IOP480 @@ -147,7 +156,6 @@ #define asyncXOFFchar 0x13 #define asyncXONchar 0x11 - /* * Minimal serial functions needed to use one of the SMC ports * as serial console interface. @@ -155,8 +163,6 @@ int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile char val; unsigned short br_reg; @@ -177,11 +183,8 @@ int serial_init (void) return (0); } - void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned short br_reg; br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); @@ -190,7 +193,6 @@ void serial_setbrg (void) out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ } - void serial_putc (const char c) { if (c == '\n') @@ -208,7 +210,6 @@ void serial_putc (const char c) } } - void serial_puts (const char *s) { while (*s) { @@ -216,7 +217,6 @@ void serial_puts (const char *s) } } - int serial_getc () { unsigned char status = 0; @@ -240,7 +240,6 @@ int serial_getc () return (0x000000ff & (int) in8 (asyncRxBufferport1)); } - int serial_tstc () { unsigned char status; @@ -264,23 +263,71 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ - /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) #if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#else #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#else #define CR0_MASK 0x3fff0000 #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 -#else -#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */ +#endif /* CONFIG_440GX */ +#elif defined(CONFIG_405EP) +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 +#else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 #define CR0_MASK 0x00001fff -#define CR0_EXTCLK_ENA 0x00000c00 +#define CR0_EXTCLK_ENA 0x000000c0 #define CR0_UDIV_POS 1 +#define UDIV_MAX 32 +#endif + +/* using serial port 0 or 1 as U-Boot console ? */ +#if defined(CONFIG_UART1_CONSOLE) +#define ACTING_UART0_BASE UART1_BASE +#define ACTING_UART1_BASE UART0_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#define UART0_SDR sdr_uart1 +#define UART1_SDR sdr_uart0 +#endif /* CONFIG_440GX */ +#else +#define ACTING_UART0_BASE UART0_BASE +#define ACTING_UART1_BASE UART1_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#endif /* CONFIG_440GX */ +#endif + +#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) +#error "External serial clock not supported on AMCC PPC405EP!" #endif #define UART_RBR 0x00 @@ -299,7 +346,7 @@ int serial_tstc () /*-----------------------------------------------------------------------------+ | Line Status Register. +-----------------------------------------------------------------------------*/ -/*#define asyncLSRport1 UART0_BASE+0x05 */ +/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ #define asyncLSRDataReady1 0x01 #define asyncLSROverrunError1 0x02 #define asyncLSRParityError1 0x04 @@ -312,11 +359,10 @@ int serial_tstc () /*-----------------------------------------------------------------------------+ | Miscellanies defines. +-----------------------------------------------------------------------------*/ -/*#define asyncTxBufferport1 UART0_BASE+0x00 */ -/*#define asyncRxBufferport1 UART0_BASE+0x00 */ +/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ +/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO /*-----------------------------------------------------------------------------+ | Fifo +-----------------------------------------------------------------------------*/ @@ -329,7 +375,6 @@ typedef struct { volatile static serial_buffer_t buf_info; #endif - #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv ) @@ -376,17 +421,18 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ - /* * Minimal serial functions needed to use one of the SMC ports * as serial console interface. */ #if defined(CONFIG_440) -int serial_init (void) +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init(void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - unsigned long reg; unsigned long udiv; unsigned short bdiv; @@ -395,7 +441,23 @@ int serial_init (void) unsigned long tmp; #endif +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; + } else { + mfsdr(UART1_SDR,reg); + reg &= ~CR0_MASK; + } +#else + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; +#endif +#else reg = mfdcr(cntrl0) & ~CR0_MASK; +#endif /* CONFIG_440GX */ #ifdef CFG_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; @@ -409,29 +471,58 @@ int serial_init (void) serial_divs (gd->baudrate, &udiv, &bdiv); #endif +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) + reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR,reg); + } else { + mtsdr (UART1_SDR,reg); + } +#else + mtsdr (UART0_SDR,reg); +#endif +#else reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); +#endif - out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ - +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif return (0); } #else /* !defined(CONFIG_440) */ +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else int serial_init (void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - unsigned long reg; unsigned long tmp; unsigned long clk; @@ -439,6 +530,17 @@ int serial_init (void) unsigned short bdiv; volatile char val; +#ifdef CONFIG_405EP + reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr (cpc0_ucr, reg); +#else /* CONFIG_405EP */ reg = mfdcr(cntrl0) & ~CR0_MASK; #ifdef CFG_EXT_SERIAL_CLOCK clk = CFG_EXT_SERIAL_CLOCK; @@ -451,35 +553,51 @@ int serial_init (void) #else tmp = CFG_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; #endif #endif - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); +#endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; - out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ - +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif return (0); } #endif /* if defined(CONFIG_440) */ +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else void serial_setbrg (void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - unsigned long tmp; unsigned long clk; unsigned long udiv; @@ -490,43 +608,100 @@ void serial_setbrg (void) #else clk = gd->cpu_clk; #endif + +#ifdef CONFIG_405EP + udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); +#else udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; +#endif /* CONFIG_405EP */ + +#if !defined(CFG_EXT_SERIAL_CLOCK) && \ + ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) ) + serial_divs (gd->baudrate, &udiv, &bdiv); + tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR, tmp); + } else { + mtsdr (UART1_SDR, tmp); + } +#else + mtsdr (UART0_SDR, tmp); +#endif + +#else + tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ - out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#endif } - +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else void serial_putc (const char c) +#endif { int i; if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else serial_putc ('\r'); +#endif /* check THRE bit, wait for transmiter available */ for (i = 1; i < 3500; i++) { - if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20) +#if defined(CONFIG_SERIAL_MULTI) + if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20) +#else + if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) +#endif break; udelay (100); } - out8 (UART0_BASE + UART_THR, c); /* put character out */ +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_THR, c); /* put character out */ +#else + out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ +#endif } - +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else void serial_puts (const char *s) +#endif { while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else serial_putc (*s++); +#endif } } - -int serial_getc () +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc (void) +#endif { unsigned char status = 0; @@ -534,7 +709,11 @@ int serial_getc () #if defined(CONFIG_HW_WATCHDOG) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ #endif /* CONFIG_HW_WATCHDOG */ - status = in8 (UART0_BASE + UART_LSR); +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif if ((status & asyncLSRDataReady1) != 0x0) { break; } @@ -542,22 +721,37 @@ int serial_getc () asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART0_BASE + UART_LSR, +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (UART0_BASE)); +#if defined(CONFIG_SERIAL_MULTI) + return (0x000000ff & (int) in8 (dev_base)); +#else + return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); +#endif } - -int serial_tstc () +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc (void) +#endif { unsigned char status; - status = in8 (UART0_BASE + UART_LSR); +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif if ((status & asyncLSRDataReady1) != 0x0) { return (1); } @@ -565,7 +759,11 @@ int serial_tstc () asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART0_BASE + UART_LSR, +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | @@ -574,8 +772,7 @@ int serial_tstc () return 0; } - -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO void serial_isr (void *arg) { @@ -589,8 +786,8 @@ void serial_isr (void *arg) } else { space = rx_get - rx_put; } - while (serial_tstc ()) { - c = serial_getc (); + while (serial_tstc_dev (ACTING_UART0_BASE)) { + c = serial_getc_dev (ACTING_UART0_BASE); if (space) { buf_info.rx_buffer[rx_put++] = c; space--; @@ -599,8 +796,8 @@ void serial_isr (void *arg) rx_put = 0; if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { /* Stop flow by setting RTS inactive */ - out8 (UART0_BASE + UART_MCR, - in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + out8 (ACTING_UART0_BASE + UART_MCR, + in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); } } buf_info.rx_put = rx_put; @@ -613,7 +810,7 @@ void serial_buffered_init (void) buf_info.rx_put = 0; buf_info.rx_get = 0; - if (in8 (UART0_BASE + UART_MSR) & 0x10) { + if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { serial_puts ("Check CTS signal present on serial port: OK.\n"); } else { serial_puts ("WARNING: CTS signal not present on serial port.\n"); @@ -624,24 +821,24 @@ void serial_buffered_init (void) (void *) &buf_info /*void *arg */ ); /* Enable "RX Data Available" Interrupt on UART */ - /* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */ - out8 (UART0_BASE + UART_IER, 0x01); + /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ + out8 (ACTING_UART0_BASE + UART_IER, 0x01); /* Set DTR active */ - out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x01); + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); /* Start flow by setting RTS active */ - out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02); + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out8 (UART0_BASE + UART_FCR, (1 << 6) | 1); + out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); } void serial_buffered_putc (const char c) { /* Wait for CTS */ #if defined(CONFIG_HW_WATCHDOG) - while (!(in8 (UART0_BASE + UART_MSR) & 0x10)) + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) WATCHDOG_RESET (); #else - while (!(in8 (UART0_BASE + UART_MSR) & 0x10)); + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); #endif serial_putc (c); } @@ -677,7 +874,7 @@ int serial_buffered_getc (void) } if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { /* Start flow by setting RTS active */ - out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02); + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); } return c; @@ -690,7 +887,6 @@ int serial_buffered_tstc (void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - #if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port @@ -703,8 +899,6 @@ int serial_buffered_tstc (void) #if (CONFIG_KGDB_SER_INDEX & 2) void kgdb_serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile char val; unsigned short br_reg; @@ -714,31 +908,29 @@ void kgdb_serial_init (void) /* * Init onboard 16550 UART */ - out8 (UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out8 (UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out8 (UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (UART1_BASE + UART_LSR); /* clear line status */ - val = in8 (UART1_BASE + UART_RBR); /* read receive buffer */ - out8 (UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ } - void putDebugChar (const char c) { if (c == '\n') serial_putc ('\r'); - out8 (UART1_BASE + UART_THR, c); /* put character out */ + out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ /* check THRE bit, wait for transfer done */ - while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20); + while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); } - void putDebugStr (const char *s) { while (*s) { @@ -746,13 +938,12 @@ void putDebugStr (const char *s) } } - int getDebugChar (void) { unsigned char status = 0; while (1) { - status = in8 (UART1_BASE + UART_LSR); + status = in8 (ACTING_UART1_BASE + UART_LSR); if ((status & asyncLSRDataReady1) != 0x0) { break; } @@ -760,17 +951,16 @@ int getDebugChar (void) asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART1_BASE + UART_LSR, + out8 (ACTING_UART1_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (UART1_BASE)); + return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); } - void kgdb_interruptible (int yes) { return; @@ -805,4 +995,87 @@ void kgdb_interruptible (int yes) #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ #endif /* CFG_CMD_KGDB */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(UART0_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(UART1_BASE)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(UART0_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(UART1_BASE); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(UART0_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(UART1_BASE, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(UART0_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(UART1_BASE, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(UART0_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(UART1_BASE)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(UART0_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(UART1_BASE)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + #endif /* CONFIG_405GP || CONFIG_405CR */