X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Ffdt.c;h=496e0285b5bd802a9445f6df7f0883623d3590a9;hb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;hp=02dece0c0ff6ffdf3c99553e04e0c9327e5e1588;hpb=eea5a743a2193ef2a05b9bc6dc447ba241416f35;p=oweals%2Fu-boot.git

diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 02dece0c0f..496e0285b5 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,7 +27,7 @@
 #include <asm/cache.h>
 #include <ppc4xx.h>
 
-#if defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
 #include <libfdt_env.h>
 #include <fdt_support.h>
@@ -35,6 +35,45 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void __ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+	int i;
+	u32 bxcr;
+	u32 ranges[EBC_NUM_BANKS * 4];
+	u32 *p = ranges;
+	char *ebc_path = "/plb/opb/ebc";
+
+	ft_cpu_setup(blob, bd);
+
+	/*
+	 * Read 4xx EBC bus bridge registers to get mappings of the
+	 * peripheral banks into the OPB/PLB address space
+	 */
+	for (i = 0; i < EBC_NUM_BANKS; i++) {
+		mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
+		bxcr = mfdcr(EBC0_CFGDATA);
+
+		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+			*p++ = i;
+			*p++ = 0;
+			*p++ = bxcr & EBC_BXCR_BAS_MASK;
+			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+		}
+	}
+
+	/* Some 405 PPC's have EBC as direct PLB child in the dts */
+	if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+		strcpy(ebc_path, "/plb/ebc");
+	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+				  (p - ranges) * sizeof(u32), 1);
+	if (rc) {
+		printf("Unable to update property EBC mappings, err=%s\n",
+		       fdt_strerror(rc));
+	}
+}
+void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+
 /*
  * Fixup all PCIe nodes by setting the device_type property
  * to "pci-endpoint" instead is "pci" for endpoint ports.
@@ -74,6 +113,7 @@ void fdt_pcie_setup(void *blob)
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	sys_info_t sys_info;
+	int off, ndepth = 0;
 
 	get_sys_info(&sys_info);
 
@@ -94,19 +134,38 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 	/*
-	 * Setup all baudrates for the UARTs
+	 * Fixup all UART clocks for CPU internal UARTs
+	 * (only these UARTs are definitely clocked by gd->uart_clk)
+	 *
+	 * These UARTs are direct childs of /plb/opb. This code
+	 * does not touch any UARTs that are connected to the ebc.
 	 */
-	do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+	off = fdt_path_offset(blob, "/plb/opb");
+	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
+		/*
+		 * process all sub nodes and stop when we are back
+		 * at the starting depth
+		 */
+		if (ndepth <= 0)
+			break;
+
+		/* only update direct childs */
+		if ((ndepth == 1) &&
+		    (fdt_node_check_compatible(blob, off, "ns16550") == 0))
+			fdt_setprop(blob, off,
+				    "clock-frequency",
+				    (void*)&(gd->uart_clk), 4);
+	}
 
 	/*
 	 * Fixup all ethernet nodes
 	 * Note: aliases in the dts are required for this
 	 */
-	fdt_fixup_ethernet(blob, bd);
+	fdt_fixup_ethernet(blob);
 
 	/*
 	 * Fixup all available PCIe nodes by setting the device_type property
 	 */
 	fdt_pcie_setup(blob);
 }
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */