X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu_init.c;h=b27567fa4d14100e2ae07fe83ee3c394da06c29b;hb=36b904a7fdc170a69eb94975b0e506dc2a73fa82;hp=1d149bc6089809f8bc81542c41fd9d7eaa90ae9c;hpb=baa3d528fe8f03c89bd9006819797db675632703;p=oweals%2Fu-boot.git diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 1d149bc608..b27567fa4d 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -23,13 +23,195 @@ #include #include -#include <405gp_enet.h> +#include #include #include +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) +DECLARE_GLOBAL_DATA_PTR; +#endif + #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) +#ifdef CFG_INIT_DCACHE_CS +# if (CFG_INIT_DCACHE_CS == 0) +# define PBxAP pb0ap +# define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 1) +# define PBxAP pb1ap +# define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 2) +# define PBxAP pb2ap +# define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 3) +# define PBxAP pb3ap +# define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 4) +# define PBxAP pb4ap +# define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 5) +# define PBxAP pb5ap +# define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 6) +# define PBxAP pb6ap +# define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 7) +# define PBxAP pb7ap +# define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +#endif /* CFG_INIT_DCACHE_CS */ + +#if defined(CFG_440_GPIO_TABLE) +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; + +void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX]) +{ + unsigned char i=0, j=0, reg_offset = 0, gpio_core; + unsigned long gpio_reg, gpio_core_add; + + for (gpio_core=0; gpio_core> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + + if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) || + ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { + + switch ((*gpio_tab)[gpio_core][i].alt_nb) { + case GPIO_SEL: + if (gpio_core == GPIO0) { + gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); + out32(GPIO0_TCR, gpio_reg); + } + + if (gpio_core == GPIO1) { + gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); + out32(GPIO1_TCR, gpio_reg); + } + + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT1: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + } + } +} +#endif /* CFG_440_GPIO_TABLE */ /* * Breath some life into the CPU... @@ -40,10 +222,34 @@ void cpu_init_f (void) { +#if defined(CONFIG_405EP) + /* + * GPIO0 setup (select GPIO or alternate function) + */ + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + + /* + * Set EMAC noise filter bits + */ + mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); +#endif /* CONFIG_405EP */ + +#if defined(CFG_440_GPIO_TABLE) + set_chip_gpio_configuration(&gpio_tab); +#endif /* CFG_440_GPIO_TABLE */ + /* * External Bus Controller (EBC) Setup */ #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! @@ -59,42 +265,43 @@ cpu_init_f (void) asm volatile(" ori 3, 3, 0xA000" ::: "r3"); asm volatile(" mtctr 3" ::: "ctr"); asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); +#endif mtebc(pb0ap, CFG_EBC_PB0AP); mtebc(pb0cr, CFG_EBC_PB0CR); #endif -#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) mtebc(pb1ap, CFG_EBC_PB1AP); mtebc(pb1cr, CFG_EBC_PB1CR); #endif -#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) mtebc(pb2ap, CFG_EBC_PB2AP); mtebc(pb2cr, CFG_EBC_PB2CR); #endif -#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) mtebc(pb3ap, CFG_EBC_PB3AP); mtebc(pb3cr, CFG_EBC_PB3CR); #endif -#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) mtebc(pb4ap, CFG_EBC_PB4AP); mtebc(pb4cr, CFG_EBC_PB4CR); #endif -#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) mtebc(pb5ap, CFG_EBC_PB5AP); mtebc(pb5cr, CFG_EBC_PB5CR); #endif -#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) mtebc(pb6ap, CFG_EBC_PB6AP); mtebc(pb6cr, CFG_EBC_PB6CR); #endif -#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) mtebc(pb7ap, CFG_EBC_PB7AP); mtebc(pb7cr, CFG_EBC_PB7CR); #endif @@ -103,7 +310,11 @@ cpu_init_f (void) unsigned long val; val = mfspr(tcr); +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + val |= 0xb8000000; /* generate system reset after 1.34 seconds */ +#else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ +#endif mtspr(tcr, val); val = mfspr(tsr); @@ -119,12 +330,30 @@ cpu_init_f (void) */ int cpu_init_r (void) { -#ifdef CONFIG_405GP - DECLARE_GLOBAL_DATA_PTR; - +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) bd_t *bd = gd->bd; unsigned long reg; +#if defined(CONFIG_405GP) uint pvr = get_pvr(); +#endif + +#ifdef CFG_INIT_DCACHE_CS + /* + * Flush and invalidate dcache, then disable CS for temporary stack. + * Afterwards, this CS can be used for other purposes + */ + dcache_disable(); /* flush and invalidate dcache */ + mtebc(PBxAP, 0); + mtebc(PBxCR, 0); /* disable CS for temporary stack */ + +#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) + /* + * Write new value into CS register + */ + mtebc(PBxAP, PBxAP_VAL); + mtebc(PBxCR, PBxCR_VAL); +#endif +#endif /* CFG_INIT_DCACHE_CS */ /* * Write Ethernetaddress into on-chip register @@ -145,6 +374,7 @@ int cpu_init_r (void) reg |= bd->bi_enetaddr[5]; out32 (EMAC_IAL, reg); +#if defined(CONFIG_405GP) /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. @@ -152,7 +382,7 @@ int cpu_init_r (void) if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { mtdcr(ecr, 0x60606000); } - -#endif /* CONFIG_405GP */ +#endif /* defined(CONFIG_405GP) */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ return (0); }