X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F4xx_pcie.c;h=3af9862bfff0dd8a5d313d7bb68c81a903035d5d;hb=feaa43f3a8f465cbf01ffa1b23b6b52431819a52;hp=da179f9c3a81daf482e4bbc8f49d76498bf07b07;hpb=5cb4af4791f61843432155142b6cfac901f66c10;p=oweals%2Fu-boot.git

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index da179f9c3a..3af9862bff 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -401,6 +401,48 @@ int ppc4xx_init_pcie(void)
 	return 0;
 }
 #else
+static void ppc4xx_setup_utl(u32 port)
+{
+	u32 utl_base;
+
+	/*
+	 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
+	 */
+	switch (port) {
+	case 0:
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
+		break;
+
+	case 1:
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
+
+		break;
+	}
+	utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+
+	/*
+	 * Set buffer allocations and then assert VRB and TXE.
+	 */
+	out_be32((u32 *)(utl_base + PEUTL_OUTTR),   0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_INTR),    0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_OPDBSZ),  0x04000000);
+	out_be32((u32 *)(utl_base + PEUTL_PBBSZ),   0x21000000);
+	out_be32((u32 *)(utl_base + PEUTL_IPHBSZ),  0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_IPDBSZ),  0x04000000);
+	out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
+	out_be32((u32 *)(utl_base + PEUTL_PCTL),    0x80800066);
+
+	out_be32((u32 *)(utl_base + PEUTL_PBCTL),   0x0800000c);
+	out_be32((u32 *)(utl_base + PEUTL_RCSTA),
+		 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
+}
+
 int ppc4xx_init_pcie(void)
 {
 	/*
@@ -480,8 +522,8 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 		val = 0x00101000;
 
 	SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
-	SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
-	SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
+	SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
+	SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
 	SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
 	SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
 
@@ -512,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 #endif /* CONFIG_405EX */
 
 int ppc4xx_init_pcie_port_hw(int port, int rootport)
-	__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
 
 /*
  * We map PCI Express configuration access into the 512MB regions
@@ -643,14 +685,12 @@ int ppc4xx_init_pcie_port(int port, int rootport)
 		return -1;
 	}
 
-#if defined(CONFIG_440SPE)
 	/*
 	 * Setup UTL registers - but only on revA!
 	 * We use default settings for revB chip.
 	 */
 	if (!ppc440spe_revB())
 		ppc4xx_setup_utl(port);
-#endif
 
 	/*
 	 * We map PCI Express configuration access into the 512MB regions