X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F4xx_pcie.c;h=3af9862bfff0dd8a5d313d7bb68c81a903035d5d;hb=feaa43f3a8f465cbf01ffa1b23b6b52431819a52;hp=167aba69608886a360565430cb0f5221d7359239;hpb=ff68f66bcb0da847845aa2fac11eba6c25938c99;p=oweals%2Fu-boot.git

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 167aba6960..3af9862bff 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -46,6 +46,20 @@ enum {
 	LNKW_X8			= 0x8
 };
 
+static int validate_endpoint(struct pci_controller *hose)
+{
+	if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+		return (is_end_point(0));
+	else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+		return (is_end_point(1));
+#if CFG_PCIE_NR_PORTS > 2
+	else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+		return (is_end_point(2));
+#endif
+
+	return 0;
+}
+
 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
 {
 	u8 *base = (u8*)hose->cfg_data;
@@ -95,6 +109,9 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
 	u8 *address;
 	*val = 0;
 
+	if (validate_endpoint(hose))
+		return 0;		/* No upstream config access */
+
 	/*
 	 * Bus numbers are relative to hose->first_busno
 	 */
@@ -150,6 +167,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 
 	u8 *address;
 
+	if (validate_endpoint(hose))
+		return 0;		/* No upstream config access */
+
 	/*
 	 * Bus numbers are relative to hose->first_busno
 	 */
@@ -381,6 +401,48 @@ int ppc4xx_init_pcie(void)
 	return 0;
 }
 #else
+static void ppc4xx_setup_utl(u32 port)
+{
+	u32 utl_base;
+
+	/*
+	 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
+	 */
+	switch (port) {
+	case 0:
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
+		break;
+
+	case 1:
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
+
+		break;
+	}
+	utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+
+	/*
+	 * Set buffer allocations and then assert VRB and TXE.
+	 */
+	out_be32((u32 *)(utl_base + PEUTL_OUTTR),   0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_INTR),    0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_OPDBSZ),  0x04000000);
+	out_be32((u32 *)(utl_base + PEUTL_PBBSZ),   0x21000000);
+	out_be32((u32 *)(utl_base + PEUTL_IPHBSZ),  0x02000000);
+	out_be32((u32 *)(utl_base + PEUTL_IPDBSZ),  0x04000000);
+	out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
+	out_be32((u32 *)(utl_base + PEUTL_PCTL),    0x80800066);
+
+	out_be32((u32 *)(utl_base + PEUTL_PBCTL),   0x0800000c);
+	out_be32((u32 *)(utl_base + PEUTL_RCSTA),
+		 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
+}
+
 int ppc4xx_init_pcie(void)
 {
 	/*
@@ -454,20 +516,14 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 {
 	u32 val;
 
-	/*
-	 * test-only:
-	 * This needs some testing and perhaps changes for
-	 * endpoint configuration. Probably no PHY reset at all, etc.
-	 * sr, 2007-10-03
-	 */
 	if (rootport)
 		val = 0x00401000;
 	else
 		val = 0x00101000;
 
 	SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
-	SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
-	SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
+	SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
+	SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
 	SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
 	SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
 
@@ -476,7 +532,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 	udelay(1000);
 
 	/* deassert the PE0_hotreset */
-	SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
+	if (is_end_point(port))
+		SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
+	else
+		SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
 
 	/* poll for phy !reset */
 	while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
@@ -495,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 #endif /* CONFIG_405EX */
 
 int ppc4xx_init_pcie_port_hw(int port, int rootport)
-	__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
 
 /*
  * We map PCI Express configuration access into the 512MB regions
@@ -595,9 +654,9 @@ int ppc4xx_init_pcie_port(int port, int rootport)
 	u32 low, high;
 
 	if (!core_init) {
-		++core_init;
 		if (ppc4xx_init_pcie())
 			return -1;
+		++core_init;
 	}
 
 	/*
@@ -626,14 +685,12 @@ int ppc4xx_init_pcie_port(int port, int rootport)
 		return -1;
 	}
 
-#if defined(CONFIG_440SPE)
 	/*
 	 * Setup UTL registers - but only on revA!
 	 * We use default settings for revB chip.
 	 */
 	if (!ppc440spe_revB())
 		ppc4xx_setup_utl(port);
-#endif
 
 	/*
 	 * We map PCI Express configuration access into the 512MB regions
@@ -812,7 +869,7 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
 	out_le32(mbase + 0x208, 0x06040001);
 
-	printf("PCIE:%d successfully set as rootpoint\n", port);
+	printf("PCIE%d: successfully set as root-complex\n", port);
 }
 
 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
@@ -883,11 +940,22 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 #endif
 	}
 
-	/* Set up 16GB inbound memory window at 0 */
+	/* Set up 64MB inbound memory window at 0 */
 	out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
 	out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
-	out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
-	out_le32(mbase + PECFG_BAR0LMPA, 0);
+
+	out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
+	out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
+
+	/* Setup BAR0 */
+	out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
+	out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
+
+	/* Disable BAR1 & BAR2 */
+	out_le32(mbase + PECFG_BAR1MPA, 0);
+	out_le32(mbase + PECFG_BAR2HMPA, 0);
+	out_le32(mbase + PECFG_BAR2LMPA, 0);
+
 	out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
 	out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
 	out_le32(mbase + PECFG_PIMEN, 0x1);
@@ -899,6 +967,9 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 	out_le16(mbase + 0x200, 0xcaad);		/* Setting vendor ID */
 	out_le16(mbase + 0x202, 0xfeed);		/* Setting device ID */
 
+	/* Set Class Code to Processor/PPC */
+	out_le32(mbase + 0x208, 0x0b200001);
+
 	attempts = 10;
 	while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
 		if (!(attempts--)) {
@@ -908,7 +979,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 		mdelay(1000);
 	}
 
-	printf("PCIE:%d successfully set as endpoint\n", port);
+	printf("PCIE%d: successfully set as endpoint\n", port);
 
 	return 0;
 }