X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F44x_spd_ddr.c;h=b9cf5cbfccaf0b8ebdfa4a32616c2ebd3674cbae;hb=328a340392a5df9aaf00792be989df73e750859e;hp=a384392406a6b5d10092195d4dda195191e17aab;hpb=a5d71e290f3673269be8eefb4ec44f53412f9461;p=oweals%2Fu-boot.git

diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index a384392406..b9cf5cbfcc 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -251,10 +251,10 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
 #define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
@@ -269,9 +269,8 @@ struct bank_param {
 typedef struct bank_param BANKPARMS;
 
 #ifdef CFG_SIMULATE_SPD_EEPROM
-extern unsigned char cfg_simulate_spd_eeprom[128];
+extern const unsigned char cfg_simulate_spd_eeprom[128];
 #endif
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
 
 static unsigned char spd_read(uchar chip, uint addr);
 static void get_spd_info(unsigned long *dimm_populated,
@@ -346,7 +345,7 @@ long int spd_sdram(void) {
 	 */
 	check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	/*
 	 * Soft-reset SDRAM controller.
 	 */
@@ -382,7 +381,7 @@ long int spd_sdram(void) {
 
 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 	/* and program tlb entries for this size (dynamic) */
-	program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 #endif
 
 	/*
@@ -646,7 +645,7 @@ static void program_rtr(unsigned long *dimm_populated,
 	unsigned char refresh_rate_type;
 	unsigned long refresh_interval;
 	unsigned long sdram_rtr;
-	PPC440_SYS_INFO sys_info;
+	PPC4xx_SYS_INFO sys_info;
 
 	/*
 	 * get the board info
@@ -722,7 +721,7 @@ static void program_tr0(unsigned long *dimm_populated,
 	unsigned long tcyc_2_0_ns_x_10;
 	unsigned long tcyc_reg;
 	unsigned long bus_period_x_10;
-	PPC440_SYS_INFO sys_info;
+	PPC4xx_SYS_INFO sys_info;
 	unsigned long residue;
 
 	/*
@@ -1017,7 +1016,7 @@ static int short_mem_test(void)
 			 */
 			for (i = 0; i < NUMMEMTESTS; i++) {
 				for (j = 0; j < NUMMEMWORDS; j++) {
-//printf("bank enabled base:%x\n", &membase[j]);
+					/* printf("bank enabled base:%x\n", &membase[j]); */
 					membase[j] = test[i][j];
 					ppcDcbf((unsigned long)&(membase[j]));
 				}
@@ -1066,7 +1065,7 @@ static void program_tr1(void)
 	unsigned char window_found;
 	unsigned char fail_found;
 	unsigned char pass_found;
-	PPC440_SYS_INFO sys_info;
+	PPC4xx_SYS_INFO sys_info;
 
 	/*
 	 * get the board info
@@ -1198,9 +1197,6 @@ static void program_tr1(void)
 	}
 
 	rdclt_average = ((max_start + max_end) >> 1);
-	if (rdclt_average >= 0x60)
-		while (1)
-			;
 
 	if (rdclt_average < 0) {
 		rdclt_average = 0;
@@ -1350,14 +1346,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 			 */
 			cr |= SDRAM_BXCR_SDBE;
 
- 			for (i = 0; i < num_banks; i++) {
+			for (i = 0; i < num_banks; i++) {
 				bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
 					(4 << 20) * bank_size_id;
 				bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
 				debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
 				      dimm_num, i, ctrl_bank_num[dimm_num]+i,
 				      bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
- 			}
+			}
 		}
 	}