X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fnios2%2Fstart.S;h=6c6f294b011a51d561e13b218330777f1fd4ae23;hb=de5b094def5d80c4355c0326cfb54b9289f7d609;hp=281d42c2123c5a1de03095681ef82bb03d45e006;hpb=5c952cf0245421feb4644f2e71487c0b2e1dbd13;p=oweals%2Fu-boot.git

diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S
index 281d42c212..6c6f294b01 100644
--- a/cpu/nios2/start.S
+++ b/cpu/nios2/start.S
@@ -39,14 +39,24 @@ _start:
 	 * just be invalidating the cache a second time. If cache
 	 * is not implemented initi behaves as nop.
 	 */
-	movhi	r4, %hi(CFG_ICACHELINE_SIZE)
-	ori	r4, r4, %lo(CFG_ICACHELINE_SIZE)
+	ori	r4, r0, %lo(CFG_ICACHELINE_SIZE)
 	movhi	r5, %hi(CFG_ICACHE_SIZE)
 	ori	r5, r5, %lo(CFG_ICACHE_SIZE)
 	mov	r6, r0
 0:	initi	r6
 	add	r6, r6, r4
 	bltu	r6, r5, 0b
+	br	_except_end	/* Skip the tramp */
+
+	/* EXCEPTION TRAMPOLINE -- the following gets copied
+	 * to the exception address (below), but is otherwise at the
+	 * default exception vector offset (0x0020).
+	 */
+_except_start:
+	movhi	et, %hi(_exception)
+	ori	et, et, %lo(_exception)
+	jmp	et
+_except_end:
 
 	/* INTERRUPTS -- for now, all interrupts masked and globally
 	 * disabled.
@@ -117,7 +127,9 @@ _cur:	movhi	r5, %hi(_cur - _start)
 _reloc:
 
 	/* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
-	 * exception address.
+	 * exception address. Define CONFIG_ROM_STUBS to prevent
+	 * the copy (e.g. exception in flash or in other
+	 * softare/firmware component).
 	 */
 #if !defined(CONFIG_ROM_STUBS)
 	movhi	r4, %hi(_except_start)
@@ -126,12 +138,14 @@ _reloc:
 	ori	r5, r5, %lo(_except_end)
 	movhi	r6, %hi(CFG_EXCEPTION_ADDR)
 	ori	r6, r6, %lo(CFG_EXCEPTION_ADDR)
+	beq	r4, r6, 7f	/* Skip if at proper addr */
 
 6:	ldwio	r7, 0(r4)
 	stwio	r7, 0(r6)
 	addi	r4, r4, 4
 	addi	r6, r6, 4
 	bne	r4, r5, 6b
+7:
 #endif
 
 	/* STACK INIT -- zero top two words for call back chain.
@@ -155,15 +169,6 @@ _reloc:
 	 */
 	br	_start
 
-	/* EXCEPTION TRAMPOLINE -- the following gets copied
-	 * to the exception address.
-	 */
-_except_start:
-	movhi	et, %hi(_exception)
-	ori	et, et, %lo(_exception)
-	jmp	et
-_except_end:
-
 
 /*
  * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
@@ -173,20 +178,20 @@ _except_end:
  * Instruction performance varies based on the core. For cores
  * with icache and static/dynamic branch prediction (II/f, II/s):
  *
- * 	Normal ALU (e.g. add, cmp, etc):	1 cycle
- * 	Branch (correctly predicted, taken):	2 cycles
+ *	Normal ALU (e.g. add, cmp, etc):	1 cycle
+ *	Branch (correctly predicted, taken):	2 cycles
  *	Negative offset is predicted (II/s).
  *
  * For cores without icache and no branch prediction (II/e):
  *
- * 	Normal ALU (e.g. add, cmp, etc):	6 cycles
- * 	Branch (no prediction):			6 cycles
+ *	Normal ALU (e.g. add, cmp, etc):	6 cycles
+ *	Branch (no prediction):			6 cycles
  *
  * For simplicity, if an instruction cache is implemented we
  * assume II/f or II/s. Otherwise, we use the II/e.
  *
  */
- 	.globl dly_clks
+	.globl dly_clks
 
 dly_clks: