X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc8xx%2Fspeed.c;h=f309f29c0493422c2c09b73c319b1f2b2efe7729;hb=6d0f6bcf337c5261c08fabe12982178c2c489d76;hp=cc011efa4dd3f3cb65910016c3df361c24a7e577;hpb=1114257c9df3fa3db39ff55dd03d1f7cbc5c0603;p=oweals%2Fu-boot.git diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index cc011efa4d..f309f29c04 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -25,7 +25,9 @@ #include #include -#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK) +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG) #define PITC_SHIFT 16 #define PITR_SHIFT 16 @@ -85,12 +87,12 @@ static __inline__ void set_msr(unsigned long msr) unsigned long measure_gclk(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; ulong timer2_val; ulong msr_val; -#ifdef CFG_8XX_XIN +#ifdef CONFIG_SYS_8XX_XIN /* dont use OSCM, only use EXTCLK/512 */ immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; #else @@ -135,7 +137,7 @@ unsigned long measure_gclk(void) immr->im_sit.sit_pitc = SPEED_PITC_INIT; immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; /* * Start measurement - disable interrupts, just in case @@ -162,9 +164,9 @@ unsigned long measure_gclk(void) timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); immr->im_sit.sit_piscr &= ~PISCR_PTE; -#if defined(CFG_8XX_XIN) +#if defined(CONFIG_SYS_8XX_XIN) /* not using OSCM, using XIN, so scale appropriately */ - return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L; + return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L; #else return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ #endif @@ -172,7 +174,28 @@ unsigned long measure_gclk(void) #endif -#if !defined(CONFIG_TQM866M) +void get_brgclk(uint sccr) +{ + uint divider = 0; + + switch((sccr&SCCR_DFBRG11)>>11){ + case 0: + divider = 1; + break; + case 1: + divider = 4; + break; + case 2: + divider = 16; + break; + case 3: + divider = 64; + break; + } + gd->brg_clk = gd->cpu_clk/divider; +} + +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) /* * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ @@ -181,8 +204,6 @@ unsigned long measure_gclk(void) */ int get_clocks (void) { - DECLARE_GLOBAL_DATA_PTR; - uint immr = get_immr (0); /* Return full IMMR contents */ volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); uint sccr = immap->im_clkrst.car_sccr; @@ -223,24 +244,24 @@ int get_clocks (void) gd->bus_clk = gd->cpu_clk / 2; } + get_brgclk(sccr); + return (0); } -#else /* CONFIG_MPC866_FAMILY */ +#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ static long init_pll_866 (long clk); /* This function sets up PLL (init_pll_866() is called) and * fills gd->cpu_clk and gd->bus_clk according to the environment - * variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk' + * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' * contains invalid value). - * This functions requires an MPC866 series CPU. + * This functions requires an MPC866 or newer series CPU. */ int get_clocks_866 (void) { - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; char tmp[64]; long cpuclk = 0; long sccr_reg; @@ -248,19 +269,22 @@ int get_clocks_866 (void) if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk)) - cpuclk = CFG_866_CPUCLK_DEFAULT; + if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) + cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; gd->cpu_clk = init_pll_866 (cpuclk); -#if defined(CFG_MEASURE_CPUCLK) +#if defined(CONFIG_SYS_MEASURE_CPUCLK) gd->cpu_clk = measure_gclk (); #endif + get_brgclk(immr->im_clkrst.car_sccr); + /* if cpu clock <= 66 MHz then set bus division factor to 1, * otherwise set it to 2 */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; + if (gd->cpu_clk <= 66000000) { sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; @@ -277,20 +301,18 @@ int get_clocks_866 (void) */ int sdram_adjust_866 (void) { - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long mamr; mamr = immr->im_memctl.memc_mamr; mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT); + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); immr->im_memctl.memc_mamr = mamr; return (0); } -/* Configure PLL for MPC866/859 CPU series +/* Configure PLL for MPC866/859/885 CPU series * PLL multiplication factor is set to the value nearest to the desired clk, * assuming a oscclk of 10 MHz. */ @@ -298,7 +320,7 @@ static long init_pll_866 (long clk) { extern void plprcr_write_866 (long); - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long n, plprcr; char mfi, mfn, mfd, s, pdf; long step_mfi, step_mfn; @@ -312,19 +334,19 @@ static long init_pll_866 (long clk) if (clk < 40000000) { s = 2; - step_mfi = CFG_866_OSCCLK / 4; + step_mfi = CONFIG_8xx_OSCLK / 4; mfd = 7; - step_mfn = CFG_866_OSCCLK / 30; + step_mfn = CONFIG_8xx_OSCLK / 30; } else if (clk < 80000000) { s = 1; - step_mfi = CFG_866_OSCCLK / 2; + step_mfi = CONFIG_8xx_OSCLK / 2; mfd = 14; - step_mfn = CFG_866_OSCCLK / 30; + step_mfn = CONFIG_8xx_OSCLK / 30; } else { s = 0; - step_mfi = CFG_866_OSCCLK; + step_mfi = CONFIG_8xx_OSCLK; mfd = 29; - step_mfn = CFG_866_OSCCLK / 30; + step_mfn = CONFIG_8xx_OSCLK / 30; } /* Calculate integer part of multiplication factor @@ -362,24 +384,23 @@ static long init_pll_866 (long clk) return (n); } -#endif /* CONFIG_MPC866_FAMILY */ +#endif /* CONFIG_8xx_CPUCLK_DEFAULT */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock */ int adjust_sdram_tbs_8xx (void) { - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long mamr; long sccr; mamr = immr->im_memctl.memc_mamr; mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); immr->im_memctl.memc_mamr = mamr; if (gd->cpu_clk < 67000000) { @@ -390,6 +411,6 @@ int adjust_sdram_tbs_8xx (void) return (0); } -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ /* ------------------------------------------------------------------------- */