X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Fspd_sdram.c;h=e501caf457af39dc4864bd84e24182fbbf8d737c;hb=d075eec500acffed5fa404a45a3e12e158d0cb33;hp=b18e8225defb3a0e3963a5f63279abc0126ba736;hpb=ea08ff6e14f9ebb8c07cfa79c51ef540eb087393;p=oweals%2Fu-boot.git diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index b18e8225de..e501caf457 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -27,7 +27,7 @@ #include #include #include - +#include #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void dma_init(void); @@ -51,20 +51,32 @@ extern int dma_xfer(void *dest, uint count, void *src); #define CFG_SUPER_BANK_INTERLEAVING 0 /* - * Convert picoseconds into clock cycles (rounding up if needed). + * Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -int -picos_to_clk(int picos) +static unsigned int +picos_to_clk(unsigned int picos) { - int clks; - - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + /* use unsigned long long to avoid rounding errors */ + const unsigned long long ULL_2e12 = 2000000000000ULL; + unsigned long long clks; + unsigned long long clks_temp; + + if (! picos) + return 0; + + clks = get_bus_freq(0) * (unsigned long long) picos; + clks_temp = clks; + clks = clks / ULL_2e12; + if (clks_temp % ULL_2e12) { clks++; } - return clks; + if (clks > 0xFFFFFFFFULL) { + clks = 0xFFFFFFFFULL; + } + + return (unsigned int) clks; } @@ -184,7 +196,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -284,9 +296,9 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. Rev1 only */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { gur->ddrioovcr = (0 | 0x80000000 /* Enable */ | 0x10000000 /* VSEL to 1.8V */ @@ -309,6 +321,10 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + #ifdef CONFIG_DDR_INTERLEAVE if (dimm_num != 1) { @@ -345,6 +361,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, #endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -374,6 +391,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -391,6 +409,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs1_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); @@ -410,6 +429,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs2_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -427,6 +447,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs3_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); @@ -936,19 +957,25 @@ unsigned int enable_ddr(unsigned int ddr_num) * Read both dimm slots and decide whether * or not to enable this controller. */ - memset((void *)&spd1,0,sizeof(spd1)); - memset((void *)&spd2,0,sizeof(spd2)); + memset((void *)&spd1, 0, sizeof(spd1)); + memset((void *)&spd2, 0, sizeof(spd2)); if (ddr_num == 1) { CFG_READ_SPD(SPD_EEPROM_ADDRESS1, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#if defined(SPD_EEPROM_ADDRESS2) CFG_READ_SPD(SPD_EEPROM_ADDRESS2, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } else { +#if defined(SPD_EEPROM_ADDRESS3) CFG_READ_SPD(SPD_EEPROM_ADDRESS3, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#endif +#if defined(SPD_EEPROM_ADDRESS4) CFG_READ_SPD(SPD_EEPROM_ADDRESS4, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } /* @@ -1093,21 +1120,26 @@ spd_sdram(void) { int memsize_ddr1_dimm1 = 0; int memsize_ddr1_dimm2 = 0; + int memsize_ddr1 = 0; + unsigned int law_size_ddr1; + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifdef CONFIG_DDR_INTERLEAVE + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; +#endif + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) int memsize_ddr2_dimm1 = 0; int memsize_ddr2_dimm2 = 0; - int memsize_total = 0; - int memsize_ddr1 = 0; int memsize_ddr2 = 0; + unsigned int law_size_ddr2; +#endif + unsigned int ddr1_enabled = 0; unsigned int ddr2_enabled = 0; - unsigned int law_size_ddr1; - unsigned int law_size_ddr2; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + int memsize_total = 0; #ifdef CONFIG_DDR_INTERLEAVE unsigned int law_size_interleaved; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, @@ -1146,12 +1178,9 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR_INTERLEAVED - | (LAWAR_SIZE & law_size_interleaved)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); +#endif debug("Interleaved memory size is 0x%08lx\n", memsize_total); #ifdef CONFIG_DDR_INTERLEAVE @@ -1182,9 +1211,11 @@ spd_sdram(void) (unsigned int)memsize_total * 1024*1024); memsize_total += memsize_ddr1_dimm1; +#if defined(SPD_EEPROM_ADDRESS2) memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, 1, 2, (unsigned int)memsize_total * 1024*1024); +#endif memsize_total += memsize_ddr1_dimm2; /* @@ -1204,12 +1235,9 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR1 - | (LAWAR_SIZE & law_size_ddr1)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); +#endif } #if (CONFIG_NUM_DDR_CONTROLLERS > 1) @@ -1234,22 +1262,18 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 2 space. */ - if (ddr1_enabled) - mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) - & 0xfffff); - else - mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - - mcm->lawar8 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR2 - | (LAWAR_SIZE & law_size_ddr2)); - debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); - debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); +#ifdef CONFIG_FSL_LAW + set_law(8, + (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), + law_size_ddr2, LAW_TRGT_IF_DDR_2); +#endif } + + debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); + #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ - debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", - memsize_ddr1, memsize_ddr2); + debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1); /* * If neither DDR controller is enabled return 0.