X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Finterrupts.c;h=49820bbd81138fdb0675d5c62bf6b8651d84ddf4;hb=0459e7d3a0a273064b738aa2e06fd7dcd35eec58;hp=1df6cdc5b9373832053e8fd509bcd5a06b9b1bc8;hpb=ffff3ae56f5842ca3679e4ce7922b819a87aad9f;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c
index 1df6cdc5b9..49820bbd81 100644
--- a/cpu/mpc86xx/interrupts.c
+++ b/cpu/mpc86xx/interrupts.c
@@ -80,6 +80,26 @@ int interrupt_init(void)
 {
 	int ret;
 
+	/*
+	 * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
+	 * implement PEX10 errata.  As INT is active high, it
+	 * will cause core to take 0x500 interrupt.
+	 *
+	 * Due to the PIC's default pass through mode, as soon
+	 * as interrupts are enabled (MSR[EE] = 1), an interrupt
+	 * will be taken and u-boot will hang.  This is due to a
+	 * hardware change (per an errata fix) on new revisions
+	 * of the board with Rev 2.x parts.
+	 *
+	 * Setting the PIC to mixed mode prevents the hang.
+	 */
+	if ((get_svr() & 0xf0) == 0x20) {
+		volatile immap_t *immr = (immap_t *)CFG_IMMR;
+		immr->im_pic.gcr = MPC86xx_PICGCR_RST;
+		while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
+		immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
+	}
+
 	/* call cpu specific function from $(CPU)/interrupts.c */
 	ret = interrupt_init_cpu(&decrementer_count);