X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fstart.S;h=20c7ebc7238bee98e06fed91cd3ea60b1df3da03;hb=f3679aa13d9f483adb38245a87ecd5c84f57a5d3;hp=040b88deebf1613a2588a597bb420a6ad92e5288;hpb=97d80fc3912e517ee40e269abf534a006025da5c;p=oweals%2Fu-boot.git diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 040b88deeb..20c7ebc723 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -115,8 +115,8 @@ _start_e500: * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe * E500: msync,isync before L1CSR0 * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, - * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], - * SPEFCSR + * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], + * SPEFCSR */ /* invalidate d-cache */ @@ -130,7 +130,6 @@ _start_e500: /* disable d-cache */ li r0,0x0 mtspr L1CSR0,r0 - isync /* invalidate i-cache */ mfspr r0,L1CSR1 @@ -144,7 +143,6 @@ _start_e500: isync /* clear registers */ - sync li r0,0 mtspr SRR0,r0 mtspr SRR1,r0 @@ -157,54 +155,43 @@ _start_e500: mtspr MCSR,r0 mtspr DEAR,r0 - mtspr DBCR0,r0 - isync + /* not needed and conflicts with some debuggers */ + /* mtspr DBCR0,r0 */ mtspr DBCR1,r0 - isync mtspr DBCR2,r0 - isync - mtspr IAC1,r0 - mtspr IAC2,r0 + /* not needed and conflicts with some debuggers */ + /* mtspr IAC1,r0 */ + /* mtspr IAC2,r0 */ mtspr DAC1,r0 mtspr DAC2,r0 mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ - isync mtspr PID0,r0 - isync mtspr PID1,r0 - isync mtspr PID2,r0 - isync - mtspr TCR,r0 mtspr BUCSR,r0 /* disable branch prediction */ - isync - - mtspr HID0,r0 - isync - mtspr HID1,r0 - isync - - mtspr MAS4,r0 - isync - mtspr MAS6,r0 + mtspr MAS4,r0 + mtspr MAS6,r0 +#if defined(CONFIG_ENABLE_36BIT_PHYS) + mtspr MAS7,r0 +#endif isync /* Setup interrupt vectors */ - lis r1,0xfff8 + lis r1,TEXT_BASE@h mtspr IVPR, r1 - li r1,0x0100 + li r1,0x0100 mtspr IVOR0,r1 /* 0: Critical input */ - li r1,0x0200 + li r1,0x0200 mtspr IVOR1,r1 /* 1: Machine check */ - li r1,0x0300 + li r1,0x0300 mtspr IVOR2,r1 /* 2: Data storage */ - li r1,0x0400 + li r1,0x0400 mtspr IVOR3,r1 /* 3: Instruction storage */ li r1,0x0500 mtspr IVOR4,r1 /* 4: External interrupt */ @@ -214,16 +201,20 @@ _start_e500: mtspr IVOR6,r1 /* 6: Program check */ li r1,0x0800 mtspr IVOR7,r1 /* 7: floating point unavailable */ - li r1,0x0c00 + li r1,0x0900 mtspr IVOR8,r1 /* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ - li r1,0x1000 + li r1,0x0a00 mtspr IVOR10,r1 /* 10: Decrementer */ - li r1,0x1400 + li r1,0x0b00 + mtspr IVOR11,r1 /* 11: Interval timer */ + li r1,0x0c00 + mtspr IVOR12,r1 /* 12: Watchdog timer */ + li r1,0x0d00 mtspr IVOR13,r1 /* 13: Data TLB error */ - li r1,0x1300 + li r1,0x0e00 mtspr IVOR14,r1 /* 14: Instruction TLB error */ - li r1,0x2000 + li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */ /* @@ -232,11 +223,23 @@ _start_e500: * Note: There is a fixup earlier for Errata CPU4 on * Rev 1 parts that must precede this MMU invalidation. */ - li r2, 0x001e - mtspr MMUCSR0, r2 + li r2, 0x001e + mtspr MMUCSR0, r2 isync - /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. + /* + * Invalidate all TLB0 entries. + */ + li r3,4 + li r4,0 + tlbivax r4,r3 + /* + * To avoid REV1 Errata CPU6 issues, make sure + * the instruction following tlbivax is not a store. + */ + + /* + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB * region before we can access any CCSR registers such as L2 * registers, Local Access Registers,etc. We will also re-allocate @@ -246,15 +249,12 @@ _start_e500: * (e.g. board//init.S) * */ - bl tlb1_entry + bl tlb1_entry mr r5,r0 - li r1,0x000f /* max 16 TLB1 entries */ - mtctr r1 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ + mtctr r4 -0: cmpwi r4,0 - beq 1f - lwzu r0,4(r5) +0: lwzu r0,4(r5) lwzu r1,4(r5) lwzu r2,4(r5) lwzu r3,4(r5) @@ -266,7 +266,6 @@ _start_e500: msync tlbwe isync - addi r4,r4,-1 bdnz 0b 1: @@ -275,8 +274,8 @@ _start_e500: lis r4, CFG_CCSRBAR_DEFAULT@h ori r4, r4, CFG_CCSRBAR_DEFAULT@l - lis r5, CFG_CCSRBAR@h - ori r5, r5, CFG_CCSRBAR@l + lis r5, CFG_CCSRBAR@h + ori r5, r5, CFG_CCSRBAR@l srwi r6,r5,12 stw r6, 0(r4) isync @@ -291,45 +290,23 @@ _start_e500: isync #endif - /* invalidate all TLB0 entries */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ - /* set up local access windows, defined at board//init.S */ lis r7,CFG_CCSRBAR@h ori r7,r7,CFG_CCSRBAR@l - bl law_entry + bl law_entry mr r6,r0 -#if defined(CONFIG_RAM_AS_FLASH) - li r1,0x0006 -#else - li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */ -#endif - mtctr r1 lwzu r5,0(r6) /* how many windows we actually use */ + mtctr r5 -#if defined(CONFIG_RAM_AS_FLASH) - li r2,0x0c48 - li r1,0x0c50 -#else li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ li r1,0x0c30 -#endif -0: cmpwi r5,0 - beq 1f - lwzu r4,4(r6) +0: lwzu r4,4(r6) lwzu r3,4(r6) stwx r4,r7,r2 stwx r3,r7,r1 - addi r5,r5,-1 addi r2,r2,0x0020 addi r1,r1,0x0020 bdnz 0b @@ -376,9 +353,12 @@ _start: isync /* Enable Time Base and Select Time Base Clock */ - li r0,0x4000 /* time base is processor clock */ + lis r0,HID0_EMCP@h /* Enable machine check */ + ori r0,r0,0x4000 /* time base is processor clock */ +#if defined(CONFIG_ENABLE_36BIT_PHYS) + ori r0,r0,0x0080 /* enable MAS7 updates */ +#endif mtspr HID0,r0 - isync #if defined(CONFIG_ADDR_STREAMING) li r0,0x3000 @@ -386,58 +366,53 @@ _start: li r0,0x1000 #endif mtspr HID1,r0 - isync /* Enable Branch Prediction */ #if defined(CONFIG_BTB) li r0,0x201 /* BBFI = 1, BPEN = 1 */ mtspr BUCSR,r0 - isync #endif #if defined(CFG_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff - mtspr dbsr,r1 /* Clear all status bits */ + mtspr DBSR,r1 /* Clear all status bits */ lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ ori r0,r0,CFG_INIT_DBCR@l - mtspr dbcr0,r0 - isync + mtspr DBCR0,r0 #endif /* L1 DCache is used for initial RAM */ mfspr r2, L1CSR0 - ori r2, r2, 0x0003 - oris r2, r2, 0x0001 - msync - isync - mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ + ori r2, r2, 0x0003 + oris r2, r2, 0x0001 + mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ isync /* Allocate Initial RAM in data cache. */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - li r2, 512 /* 512*32=16K */ - mtctr r2 + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + li r2, 512 /* 512*32=16K */ + mtctr r2 li r0, 0 1: dcbz r0, r3 - dcbtls 0,r0, r3 - addi r3, r3, 32 - bdnz 1b + dcbtls 0,r0, r3 + addi r3, r3, 32 + bdnz 1b #ifndef CFG_RAMBOOT - /* Calculate absolute address in FLASH and jump there */ + /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 blr in_flash: -#endif /* CFG_RAMBOOT */ +#endif /* CFG_RAMBOOT */ /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h @@ -457,8 +432,7 @@ in_flash: bl cpu_init_f bl icache_enable bl board_init_f - sync - + isync /* --FIXME-- machine check with MCSRRn and rfmci */ @@ -515,105 +489,84 @@ ProgramCheck: /* No FPU on MPC85xx. This exception is not supposed to happen. */ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) - STD_EXCEPTION(0x0900, Decrementer, timer_interrupt) - STD_EXCEPTION(0x0a00, Trap_0a, UnknownException) - STD_EXCEPTION(0x0b00, Trap_0b, UnknownException) - . = 0x0c00 + . = 0x0900 /* * r0 - SYSCALL number * r3-... arguments */ SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ - ori r12,r12,0 - - cmplw 0, r0, r12 - bge 1f - - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ - add r11,r11,r0 - lwz r11,0(r11) - - li r20,0xd00-4 /* Get stack pointer */ - lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ - li r0,0xc00+_end_back-SystemCall - cmplw 0, r0, r12 /* Check stack overflow */ - bgt 1f - stw r12,0(r20) - - mflr r0 - stw r0,0(r12) - mfspr r0,SRR0 - stw r0,4(r12) - mfspr r0,SRR1 - stw r0,8(r12) - - li r12,0xc00+_back-SystemCall - mtlr r12 - mtspr SRR0,r11 - -1: SYNC + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ + ori r12,r12,0 + + cmplw 0, r0, r12 + bge 1f + + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + add r11,r11,r0 + lwz r11,0(r11) + + li r20,0xd00-4 /* Get stack pointer */ + lwz r12,0(r20) + subi r12,r12,12 /* Adjust stack pointer */ + li r0,0xc00+_end_back-SystemCall + cmplw 0, r0, r12 /* Check stack overflow */ + bgt 1f + stw r12,0(r20) + + mflr r0 + stw r0,0(r12) + mfspr r0,SRR0 + stw r0,4(r12) + mfspr r0,SRR1 + stw r0,8(r12) + + li r12,0xc00+_back-SystemCall + mtlr r12 + mtspr SRR0,r11 + +1: SYNC rfi _back: - mfmsr r11 /* Disable interrupts */ - li r12,0 - ori r12,r12,MSR_EE - andc r11,r11,r12 - SYNC /* Some chip revs need this... */ - mtmsr r11 + mfmsr r11 /* Disable interrupts */ + li r12,0 + ori r12,r12,MSR_EE + andc r11,r11,r12 + SYNC /* Some chip revs need this... */ + mtmsr r11 SYNC - li r12,0xd00-4 /* restore regs */ - lwz r12,0(r12) + li r12,0xd00-4 /* restore regs */ + lwz r12,0(r12) - lwz r11,0(r12) - mtlr r11 - lwz r11,4(r12) - mtspr SRR0,r11 - lwz r11,8(r12) - mtspr SRR1,r11 + lwz r11,0(r12) + mtlr r11 + lwz r11,4(r12) + mtspr SRR0,r11 + lwz r11,8(r12) + mtspr SRR1,r11 - addi r12,r12,12 /* Adjust stack pointer */ - li r20,0xd00-4 - stw r12,0(r20) + addi r12,r12,12 /* Adjust stack pointer */ + li r20,0xd00-4 + stw r12,0(r20) SYNC rfi _end_back: - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, PIT, PITException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) + STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) + STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) + STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) - .globl _end_of_vectors + .globl _end_of_vectors _end_of_vectors: @@ -754,7 +707,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3,L1CSR1 - srwi r3, r3, 31 /* >>31 => select bit 0 */ + andi. r3,r3,1 blr .globl dcache_enable @@ -787,7 +740,7 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3,L1CSR0 - srwi r3, r3, 31 /* >>31 => select bit 0 */ + andi. r3,r3,1 blr .globl get_pir @@ -922,6 +875,18 @@ ppcDcbi: dcbi r0,r3 blr +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + /*------------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ @@ -1022,6 +987,11 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. @@ -1095,72 +1065,69 @@ clear_bss: * r3: dest_addr * r7: source address, r8: end address, r9: target address */ - .globl trap_init + .globl trap_init trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ - mflr r4 /* save link register */ + mflr r4 /* save link register */ 1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b /* * relocate `hdlr' and `int_return' entries */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + lis r7,0x0 + mtspr IVPR, r7 - mtlr r4 /* restore link register */ + mtlr r4 /* restore link register */ blr /* * Function: relocate entries for one exception vector */ trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) blr @@ -1176,7 +1143,7 @@ unlock_ram_in_cache: dcbi r0, r3 addi r3, r3, 32 bdnz 1b - sync /* Wait for all icbi to complete on bus */ + sync /* Wait for all icbi to complete on bus */ isync blr #endif