X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fstart.S;h=20c7ebc7238bee98e06fed91cd3ea60b1df3da03;hb=6743105988fc44d5b0d30388c790607835aae7a6;hp=dd8189931a2130d74f8199c6dcaf42127f7c00bd;hpb=d9b94f28a442b0013caef99de084d7b72e2d4607;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index dd8189931a..20c7ebc723 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -155,11 +155,13 @@ _start_e500:
 	mtspr	MCSR,r0
 	mtspr	DEAR,r0
 
-	mtspr	DBCR0,r0
+	/* not needed and conflicts with some debuggers */
+	/* mtspr	DBCR0,r0 */
 	mtspr	DBCR1,r0
 	mtspr	DBCR2,r0
-	mtspr	IAC1,r0
-	mtspr	IAC2,r0
+	/* not needed and conflicts with some debuggers */
+	/* mtspr	IAC1,r0 */
+	/* mtspr	IAC2,r0 */
 	mtspr	DAC1,r0
 	mtspr	DAC2,r0
 
@@ -207,8 +209,8 @@ _start_e500:
 	li	r1,0x0b00
 	mtspr	IVOR11,r1	/* 11: Interval timer */
 	li	r1,0x0c00
-	mtspr	IVOR12,r1	/* 11: Watchdog timer */
-	li	r10,0x0d00
+	mtspr	IVOR12,r1	/* 12: Watchdog timer */
+	li	r1,0x0d00
 	mtspr	IVOR13,r1	/* 13: Data TLB error */
 	li	r1,0x0e00
 	mtspr	IVOR14,r1	/* 14: Instruction TLB error */
@@ -249,13 +251,10 @@ _start_e500:
 	 */
 	bl	tlb1_entry
 	mr	r5,r0
-	li	r1,0x0020	/* max 16 TLB1 plus some TLB0 entries */
-	mtctr	r1
 	lwzu	r4,0(r5)	/* how many TLB1 entries we actually use */
+	mtctr	r4
 
-0:	cmpwi	r4,0
-	beq	1f
-	lwzu	r0,4(r5)
+0:	lwzu	r0,4(r5)
 	lwzu	r1,4(r5)
 	lwzu	r2,4(r5)
 	lwzu	r3,4(r5)
@@ -267,7 +266,6 @@ _start_e500:
 	msync
 	tlbwe
 	isync
-	addi	r4,r4,-1
 	bdnz	0b
 
 1:
@@ -299,20 +297,16 @@ _start_e500:
 
 	bl	law_entry
 	mr	r6,r0
-	li	r1,0x0007	/* 8 LAWs, but reserve one for boot-over-rio-or-pci */
-	mtctr	r1
 	lwzu	r5,0(r6)	/* how many windows we actually use */
+	mtctr	r5
 
 	li	r2,0x0c28	/* the first pair is reserved for boot-over-rio-or-pci */
 	li	r1,0x0c30
 
-0:	cmpwi	r5,0
-	beq	1f
-	lwzu	r4,4(r6)
+0:	lwzu	r4,4(r6)
 	lwzu	r3,4(r6)
 	stwx	r4,r7,r2
 	stwx	r3,r7,r1
-	addi	r5,r5,-1
 	addi	r2,r2,0x0020
 	addi	r1,r1,0x0020
 	bdnz	0b
@@ -713,7 +707,7 @@ icache_disable:
 	.globl	icache_status
 icache_status:
 	mfspr	r3,L1CSR1
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl	dcache_enable
@@ -746,7 +740,7 @@ dcache_disable:
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3,L1CSR0
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl get_pir
@@ -993,6 +987,11 @@ relocate_code:
 7:	sync			/* Wait for all icbi to complete on bus */
 	isync
 
+	/*
+	 * Re-point the IVPR at RAM
+	 */
+	mtspr	IVPR,r10
+
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.