X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fstart.S;h=10fe93629c3badfec8d7c3189e47faac7da122ec;hb=ae9e1b579ea2ce23e531fd59a52423fd18effe77;hp=e8e5eb297de7cf97aacac084b5bcf091b1015e01;hpb=f58934551e052db5a1f33f53dcc9cbf6fcb72910;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e8e5eb297d..10fe93629c 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -89,7 +89,7 @@ _start_e500:
 	/* L1 */
 	li	r0,2
 	mtspr	L1CSR0,r0	/* invalidate d-cache */
-	mtspr	L1CSR1,r0 	/* invalidate i-cache */
+	mtspr	L1CSR1,r0	/* invalidate i-cache */
 
 	mfspr	r1,DBSR
 	mtspr	DBSR,r1		/* Clear all valid bits */
@@ -188,11 +188,12 @@ _start_e500:
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
 
-	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+	/* Align the mapping to 16MB */
+	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
 
-	lis     r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	lis     r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 
 	mtspr   MAS0,r6
 	mtspr   MAS1,r7
@@ -757,51 +758,6 @@ in32r:
 	lwbrx	r3,r0,r3
 	blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcDcbf */
-/* Description:	 Data Cache block flush */
-/* Input:	 r3 = effective address */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcDcbf
-ppcDcbf:
-	dcbf	r0,r3
-	blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcDcbi */
-/* Description:	 Data Cache block Invalidate */
-/* Input:	 r3 = effective address */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcDcbi
-ppcDcbi:
-	dcbi	r0,r3
-	blr
-
-/*--------------------------------------------------------------------------
- * Function:	 ppcDcbz
- * Description:	 Data Cache block zero.
- * Input:	 r3 = effective address
- * Output:	 none.
- *-------------------------------------------------------------------------- */
-
-	.globl	ppcDcbz
-ppcDcbz:
-	dcbz	r0,r3
-	blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcSync */
-/* Description:	 Processor Synchronize */
-/* Input:	 none. */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcSync
-ppcSync:
-	sync
-	blr
-
 /*------------------------------------------------------------------------------*/
 
 /*
@@ -1037,7 +993,6 @@ trap_reloc:
 
 	blr
 
-#ifdef CFG_INIT_RAM_LOCK
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
@@ -1047,11 +1002,20 @@ unlock_ram_in_cache:
 	andi.	r4,r4,0x1ff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
-1:	icbi	r0,r3
-	dcbi	r0,r3
+1:	dcbi	r0,r3
 	addi	r3,r3,CFG_CACHELINE_SIZE
 	bdnz	1b
-	sync			/* Wait for all icbi to complete on bus */
+	sync
+
+	/* Invalidate the TLB entries for the cache */
+	lis	r3,CFG_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_INIT_RAM_ADDR@l
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
 	isync
 	blr
-#endif