X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fspd_sdram.c;h=abc63c414bd70a3f937906262b84718151bc65e6;hb=f58934551e052db5a1f33f53dcc9cbf6fcb72910;hp=553f736a56a07d2d64bf21166a96eef900ce522d;hpb=bb701283a8dcb2521000fe437f19a83cadc98b02;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 553f736a56..abc63c414b 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -27,6 +27,7 @@
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -1022,7 +1023,6 @@ spd_sdram(void)
 static unsigned int
 setup_laws_and_tlbs(unsigned int memsize)
 {
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 	unsigned int tlb_size;
 	unsigned int law_size;
 	unsigned int ram_tlb_index;
@@ -1071,22 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
 	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
 	while (ram_tlb_address < (memsize * 1024 * 1024)
 	      && ram_tlb_index < 16) {
-		mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
-		mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
-		mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-				      0, 0, 0, 0, 0, 0, 0, 0));
-		mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-				      0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
-		asm volatile("isync;msync;tlbwe;isync");
-
-		debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
-		debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
-		debug("DDR: MAS2=0x%08x\n",
-		      TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-				0, 0, 0, 0, 0, 0, 0, 0));
-		debug("DDR: MAS3=0x%08x\n",
-		      TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-				0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+		set_tlb(1, ram_tlb_address, ram_tlb_address,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, ram_tlb_index, tlb_size, 1);
 
 		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
 		ram_tlb_index++;
@@ -1101,12 +1088,10 @@ setup_laws_and_tlbs(unsigned int memsize)
 	/*
 	 * Set up LAWBAR for all of DDR.
 	 */
-	ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-	ecm->lawar1 = (LAWAR_EN
-		       | LAWAR_TRGT_IF_DDR
-		       | (LAWAR_SIZE & law_size));
-	debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
-	debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
+
+#ifdef CONFIG_FSL_LAW
+	set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
+#endif
 
 	/*
 	 * Confirm that the requested amount of memory was mapped.