X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc83xx%2Fcpu.c;h=e38a3722ca25f6fc7c8f082cbb787f770b6d28e5;hb=a93c92cddaedd5f0720e0da15c6664f7a688b582;hp=94d1a137e27cc4cf36de904ff5c46824c738500c;hpb=dd35479a50f6c7c31ea491c07c5200c6dfd06a24;p=oweals%2Fu-boot.git diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 94d1a137e2..e38a3722ca 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -32,6 +32,13 @@ #include #include #include +#include +#include +#include +#ifdef CONFIG_BOOTCOUNT_LIMIT +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +51,6 @@ int checkcpu(void) char buf[32]; int i; -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} const struct cpu_type { char name[15]; u32 partid; @@ -67,7 +73,7 @@ int checkcpu(void) CPU_TYPE_ENTRY(8379), }; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; puts("CPU: "); @@ -124,8 +130,8 @@ int checkcpu(void) * The 'dummy' variable is used to increment the MAD. 'dummy' is * supposed to be a pointer to the memory of the device being * programmed by the UPM. The data in the MDR is written into - * memory and the MAD is incremented every time there's a read - * from 'dummy'. Unfortunately, the current prototype for this + * memory and the MAD is incremented every time there's a write + * to 'dummy'. Unfortunately, the current prototype for this * function doesn't allow for passing the address of this * device, and changing the prototype will break a number lots * of other code, so we need to use a round-about way of finding @@ -147,9 +153,8 @@ int checkcpu(void) */ void upmconfig (uint upm, uint *table, uint size) { -#if defined(CONFIG_MPC834X) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbus = &immap->lbus; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbus = &immap->lbus; volatile uchar *dummy = NULL; const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ @@ -174,16 +179,13 @@ void upmconfig (uint upm, uint *table, uint size) for (i = 0; i < size; i++) { lbus->mdr = table[i]; __asm__ __volatile__ ("sync"); - *dummy; /* Write the value to memory and increment MAD */ + *dummy = 0; /* Write the value to memory and increment MAD */ __asm__ __volatile__ ("sync"); + while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); } /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ *mxmr &= 0xCFFFFFC0; -#else - printf("Error: %s() not defined for this configuration.\n", __FUNCTION__); - hang(); -#endif } @@ -195,7 +197,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr; #endif - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef MPC83xx_RESET /* Interrupts and MMU off */ @@ -234,7 +236,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ - addr = CFG_RESET_ADDRESS; + addr = CONFIG_SYS_RESET_ADDRESS; printf("resetting the board."); printf("\n"); @@ -265,7 +267,7 @@ void watchdog_reset (void) int re_enable = disable_interrupts(); /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->wdt.swsrr = 0x556c; immr->wdt.swsrr = 0xaa39; @@ -274,107 +276,61 @@ void watchdog_reset (void) } #endif -#if defined(CONFIG_DDR_ECC) -void dma_init(void) +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 status = swab32(dma->dmasr0); - volatile u32 dmamr0 = swab32(dma->dmamr0); - - debug("DMA-init\n"); - - /* initialize DMASARn, DMADAR and DMAABCRn */ - dma->dmadar0 = (u32)0; - dma->dmasar0 = (u32)0; - dma->dmabcr0 = 0; - - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* clear CS bit */ - dmamr0 &= ~DMA_CHANNEL_START; - dma->dmamr0 = swab32(dmamr0); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* while the channel is busy, spin */ - while(status & DMA_CHANNEL_BUSY) { - status = swab32(dma->dmasr0); - } +#if defined(CONFIG_UEC_ETH) + uec_standard_init(bis); +#endif - debug("DMA-init end\n"); +#if defined(CONFIG_TSEC_ENET) + tsec_standard_init(bis); +#endif + return 0; } -uint dma_check(void) +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 status = swab32(dma->dmasr0); - volatile u32 byte_count = swab32(dma->dmabcr0); - - /* while the channel is busy, spin */ - while (status & DMA_CHANNEL_BUSY) { - status = swab32(dma->dmasr0); - } - - if (status & DMA_CHANNEL_TRANSFER_ERROR) { - printf ("DMA Error: status = %x @ %d\n", status, byte_count); - } - - return status; +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else + return 0; +#endif } -int dma_xfer(void *dest, u32 count, void *src) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 dmamr0; +#ifdef CONFIG_BOOTCOUNT_LIMIT - /* initialize DMASARn, DMADAR and DMAABCRn */ - dma->dmadar0 = swab32((u32)dest); - dma->dmasar0 = swab32((u32)src); - dma->dmabcr0 = swab32(count); - - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* init direct transfer, clear CS bit */ - dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT | - DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B | - DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN); +#if !defined(CONFIG_MPC8360) +#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" +#endif - dma->dmamr0 = swab32(dmamr0); +#if !defined(CONFIG_BOOTCOUNT_ADDR) +#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) +#endif - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); +#include - /* set CS to start DMA transfer */ - dmamr0 |= DMA_CHANNEL_START; - dma->dmamr0 = swab32(dmamr0); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - return ((int)dma_check()); +void bootcount_store (ulong a) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + out_be32 (reg, a); + out_be32 (reg + 4, BOOTCOUNT_MAGIC); } -#endif /*CONFIG_DDR_ECC*/ - -#ifdef CONFIG_TSEC_ENET -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname); -int cpu_eth_init(bd_t *bis) +ulong bootcount_load (void) { -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif - return 0; + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + + if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32 (reg); } -#endif +#endif /* CONFIG_BOOTCOUNT_LIMIT */