X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc8260%2Fpci.c;h=75c6ab298566a7eef530940300081bcc9d963bca;hb=f2b07ebd32e42a5b1126c98efc768ddb8908de62;hp=f068e8e50da8b4749de028993929eb660b01c89e;hpb=d4326aca187b965b6c96fee85cb6b98b6e5fe79c;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index f068e8e50d..75c6ab2985 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -2,6 +2,10 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -29,6 +33,11 @@
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
 #include <asm/io.h>
+
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *   Local->PCI map (from CPU)				   controlled by
  *   MPC826x master window
@@ -230,9 +239,6 @@ static inline void pci_outl (u32 addr, u32 data)
 
 void pci_mpc8250_init (struct pci_controller *hose)
 {
-#ifdef CONFIG_MPC8266ADS
-	DECLARE_GLOBAL_DATA_PTR;
-#endif
 	u16 tempShort;
 
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -248,6 +254,28 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_siu_conf.sc_siumcr =
 		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 		| SIUMCR_LBPC01;
+#elif defined CONFIG_MPC8272
+	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+				  ~SIUMCR_BBD &
+				  ~SIUMCR_ESE &
+				  ~SIUMCR_PBSE &
+				  ~SIUMCR_CDIS &
+				  ~SIUMCR_DPPC11 &
+				  ~SIUMCR_L2CPC11 &
+				  ~SIUMCR_LBPC11 &
+				  ~SIUMCR_APPC11 &
+				  ~SIUMCR_CS10PC11 &
+				  ~SIUMCR_BCTLC11 &
+				  ~SIUMCR_MMR11)
+				  | SIUMCR_DPPC11
+				  | SIUMCR_L2CPC01
+				  | SIUMCR_LBPC00
+				  | SIUMCR_APPC10
+				  | SIUMCR_CS10PC00
+				  | SIUMCR_BCTLC00
+				  | SIUMCR_MMR11;
+#elif defined(CONFIG_TQM8272)
+/* nothing to do for this Board here */
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -290,7 +318,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
 	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
 	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
 #endif
@@ -300,7 +328,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 
 	/* give it some time */
 	{
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 		/* Give the PCI cards more time to initialize before query
 		   This might be good for other boards also
 		 */
@@ -344,7 +372,11 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */
 
 	/* See above for description - puts PCI request as highest priority */
+#ifdef CONFIG_MPC8272
+	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
+#else
 	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
+#endif
 
 	/* Park the bus on the PCI */
 	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
@@ -370,7 +402,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	hose->last_busno = 0xff;
 
 	/* System memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
 	pci_set_region (hose->regions + 0,
 			PCI_SLV_MEM_BUS,
 			PCI_SLV_MEM_LOCAL,
@@ -383,7 +415,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 #endif
 
 	/* PCI memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 	pci_set_region (hose->regions + 1,
 			PCI_MSTR_MEMIO_BUS,
 			PCI_MSTR_MEMIO_LOCAL,