X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc8260%2Fcpu_init.c;h=1d527734456d7c878825a4877ef9ad455039f5ec;hb=f9edcc10e6cb497dd7dcbaf691cfd1859abae27a;hp=9f9369ab3af556474fe175ff04adeccdfdbb0234;hpb=c609719b8d1b2dca590e0ed499016d041203e403;p=oweals%2Fu-boot.git diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 9f9369ab3a..1d52773445 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -26,6 +26,12 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) +extern unsigned long board_get_cpu_clk_f (void); +#endif + static void config_8260_ioports (volatile immap_t * immr) { int portnum; @@ -70,24 +76,25 @@ static void config_8260_ioports (volatile immap_t * immr) uint tpmsk = ~pmsk; /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. + * the (somewhat confused) paragraph at the + * bottom of page 35-5 warns that there might + * be "unknown behaviour" when programming + * PSORx and PDIRx, if PPARx = 1, so I + * decided this meant I had to disable the + * dedicated function first, and enable it + * last. */ iop->ppar &= tpmsk; iop->psor = (iop->psor & tpmsk) | psor; + iop->podr = (iop->podr & tpmsk) | podr; iop->pdat = (iop->pdat & tpmsk) | pdat; iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->podr = (iop->podr & tpmsk) | podr; iop->ppar |= ppar; } } } +#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask)) /* * Breath some life into the CPU... * @@ -97,13 +104,17 @@ static void config_8260_ioports (volatile immap_t * immr) */ void cpu_init_f (volatile immap_t * immr) { - DECLARE_GLOBAL_DATA_PTR; - +#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ + uint sccr; +#endif +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) + unsigned long cpu_clk; +#endif volatile memctl8260_t *memctl = &immr->im_memctl; extern void m8260_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -113,25 +124,45 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrst.car_rsr = RSR_ALLBITS; /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CFG_RMR; + immr->im_clkrst.car_rmr = CONFIG_SYS_RMR; /* BCR - Bus Configuration Register (4-25) */ - immr->im_siu_conf.sc_bcr = CFG_BCR; +#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE) + if (immr->im_siu_conf.sc_bcr & BCR_EBM) { + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010); + } else { + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010); + } +#else + immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR; +#endif /* SIUMCR - contains debug pin configuration (4-31) */ - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; +#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH) + cpu_clk = board_get_cpu_clk_f (); + if (cpu_clk >= 100000000) { + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000); + } else { + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000); + } +#else + immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; +#endif config_8260_ioports (immr); /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CFG_TMCNTSC; + immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC; /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ /* System clock control register (9-8) */ - immr->im_clkrst.car_sccr = CFG_SCCR; + sccr = immr->im_clkrst.car_sccr & + (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); + immr->im_clkrst.car_sccr = sccr | + (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); #endif /* !CONFIG_COGENT */ /* @@ -143,70 +174,71 @@ void cpu_init_f (volatile immap_t * immr) * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; + /* the PS came from the HRCW, don´t change it */ + memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK); + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; + memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; + memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM) - memctl->memc_or8 = CFG_OR8_PRELIM; - memctl->memc_br8 = CFG_BR8_PRELIM; +#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM) + memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM; + memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM; #endif -#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM) - memctl->memc_or9 = CFG_OR9_PRELIM; - memctl->memc_br9 = CFG_BR9_PRELIM; +#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM) + memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM; + memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM; #endif -#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM) - memctl->memc_or10 = CFG_OR10_PRELIM; - memctl->memc_br10 = CFG_BR10_PRELIM; +#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM) + memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM; + memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM; #endif -#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM) - memctl->memc_or11 = CFG_OR11_PRELIM; - memctl->memc_br11 = CFG_BR11_PRELIM; +#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM) + memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM; + memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM; #endif m8260_cpm_reset (); @@ -217,11 +249,9 @@ void cpu_init_f (volatile immap_t * immr) */ int cpu_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - immr->im_cpm.cp_rccr = CFG_RCCR; + immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; return (0); } @@ -231,8 +261,6 @@ int cpu_init_r (void) */ int prt_8260_rsr (void) { - DECLARE_GLOBAL_DATA_PTR; - static struct { ulong mask; char *desc; @@ -250,7 +278,7 @@ int prt_8260_rsr (void) int i; char *sep; - puts ("MPC8260 Reset Status:"); + puts (CPU_ID_STR " Reset Status:"); sep = " "; for (i = 0; i < n; i++)