X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc5xxx%2Fstart.S;h=defe77d75f2f49aebc2c38066e4d1f741779e05a;hb=9b827cf1720acda2473afa516956eab6f7cca9a1;hp=26811e11ad7606cd040069bbb86cc745f2987e78;hpb=b98fff1d6acc57cc54f01740028535ac095237cd;p=oweals%2Fu-boot.git diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 26811e11ad..defe77d75f 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -29,7 +29,7 @@ #include #include -#define CONFIG_MPC5XXX 1 /* needed for Linux kernel header files */ +#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include @@ -103,56 +103,58 @@ boot_cold: boot_warm: mfmsr r5 /* save msr contents */ -#if defined(CFG_LOWBOOT) -#if defined(CFG_RAMBOOT) -#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT -#endif /* CFG_RAMBOOT */ - lis r4, CFG_DEFAULT_MBAR@h - lis r3, 0x0000FF00@h - ori r3, r3, 0x0000FF00@l - stw r3, 0x4(r4) - lis r3, 0x0000FFFF@h - ori r3, r3, 0x0000FFFF@l - stw r3, 0x8(r4) - lis r3, 0x00047800@h - ori r3, r3, 0x00047800@l - stw r3, 0x300(r4) + /* Move CSBoot and adjust instruction pointer */ + /*--------------------------------------------------------------*/ + +#if defined(CONFIG_SYS_LOWBOOT) +# if defined(CONFIG_SYS_RAMBOOT) +# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT +# endif /* CONFIG_SYS_RAMBOOT */ +# if defined(CONFIG_MGT5100) +# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100 +# endif /* CONFIG_MGT5100 */ + lis r4, CONFIG_SYS_DEFAULT_MBAR@h + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l + stw r3, 0x4(r4) /* CS0 start */ + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l + stw r3, 0x8(r4) /* CS0 stop */ lis r3, 0x02010000@h ori r3, r3, 0x02010000@l - stw r3, 0x54(r4) + stw r3, 0x54(r4) /* CS0 and Boot enable */ - lis r3, lowboot_reentry@h - ori r3, r3, lowboot_reentry@l + lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ + ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ mtlr r3 - blr /* jump to flash based address */ + blr lowboot_reentry: - lis r3, 0x0000FF00@h - ori r3, r3, 0x0000FF00@l - stw r3, 0x4c(r4) - lis r3, 0x0000FFFF@h - ori r3, r3, 0x0000FFFF@l - stw r3, 0x50(r4) - lis r3, 0x00047800@h - ori r3, r3, 0x00047800@l - stw r3, 0x300(r4) + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l + stw r3, 0x4c(r4) /* Boot start */ + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l + stw r3, 0x50(r4) /* Boot stop */ lis r3, 0x02000001@h ori r3, r3, 0x02000001@l - stw r3, 0x54(r4) -#endif /* CFG_LOWBOOT */ + stw r3, 0x54(r4) /* Boot enable, CS0 disable */ +#endif /* CONFIG_SYS_LOWBOOT */ -#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) - lis r3, CFG_MBAR@h - ori r3, r3, CFG_MBAR@l +#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) + lis r3, CONFIG_SYS_MBAR@h + ori r3, r3, CONFIG_SYS_MBAR@l #if defined(CONFIG_MPC5200) + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 #endif #if defined(CONFIG_MGT5100) rlwinm r3, r3, 17, 15, 31 #endif - lis r4, CFG_DEFAULT_MBAR@h + lis r4, CONFIG_SYS_DEFAULT_MBAR@h stw r3, 0(r4) -#endif /* CFG_DEFAULT_MBAR */ +#endif /* CONFIG_SYS_DEFAULT_MBAR */ /* Initialise the MPC5xxx processor core */ /*--------------------------------------------------------------*/ @@ -163,9 +165,9 @@ lowboot_reentry: /*--------------------------------------------------------------*/ /* set up stack in on-chip SRAM */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - ori r1, r3, CFG_INIT_SP_OFFSET + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -206,7 +208,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -225,7 +227,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -398,13 +400,13 @@ init_5xxx_core: /* HID0 also contains cache control */ /*--------------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 @@ -550,6 +552,11 @@ dcache_status: rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 blr + .globl get_svr +get_svr: + mfspr r3, SVR + blr + .globl get_pvr get_pvr: mfspr r3, PVR @@ -575,16 +582,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */