X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc5xxx%2Fpci_mpc5200.c;h=225738a0731c7ee6631c5d4648d5c6d0b4c0bc89;hb=3e303f748cf57fb23e8ec95ab7eac0074be50e2b;hp=2cfa11ce272e50e154dc42930a86679e83662dac;hpb=5e4b3361bc0ccb2138569f872be60165ebeefb57;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 2cfa11ce27..225738a073 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -31,8 +31,8 @@
 #include <mpc5xxx.h>
 
 /* System RAM mapped over PCI */
-#define CONFIG_PCI_MEMORY_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)
 
 /* PCIIWCR bit fields */
@@ -93,7 +93,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 		       CONFIG_PCI_MEMORY_BUS,
 		       CONFIG_PCI_MEMORY_PHYS,
 		       CONFIG_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
@@ -125,27 +125,27 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 
 	/* Set cache line size */
 	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
-		(CFG_CACHELINE_SIZE / 4);
+		(CONFIG_SYS_CACHELINE_SIZE / 4);
 
 	/* Map MBAR to PCI space */
-	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
-	*(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
+	*(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
+	*(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
 
 	/* Map RAM to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 
-	/* Enable snooping for RAM */
-	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
-	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
-
 	/* Park XLB on PCI */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 
 	/* Disable interrupts from PCI controller */
 	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
-	*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
+	*(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);
+
+	/* Set PCI retry counter to 0 = infinite retry. */
+	/* The default of 255 is too short for slow devices. */
+	*(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
 
 	/* Disable initiator windows */
 	*(vu_long *)MPC5XXX_PCI_IWCR = 0;