X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc5xxx%2Fcpu_init.c;h=bc6201ec0ac1abf9a2723fe1bf991fc9666b4a52;hb=16116ddd0d0158f4e91c91dc979b845b6e98a99d;hp=7322027e8b2592857c9d551a26acf9df026d6a0c;hpb=945af8d723a29e9b6289d84250745ed0dc16fc81;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 7322027e8b..bc6201ec0a 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -24,13 +24,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
-#if defined(CONFIG_MGT5100)
-#define START_REG(start)	((start) >> 15)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 15)
-#elif defined(CONFIG_MPC5200)
-#define START_REG(start)	((start) >> 16)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
-#endif
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Breath some life into the CPU...
@@ -40,8 +34,6 @@
  */
 void cpu_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long addecr = (1 << 25); /* Boot_CS */
 #if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
 	addecr |= (1 << 22); /* SDRAM enable */
@@ -131,7 +123,7 @@ void cpu_init_f (void)
 #endif
 
 #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
-	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
 	*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
 	addecr |= (1 << 27);
 #endif
@@ -155,6 +147,39 @@ void cpu_init_f (void)
 #if defined(CFG_GPS_PORT_CONFIG)
 	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
 #endif
+
+#if defined(CONFIG_MPC5200)
+	/* enable timebase */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
+
+	/* Enable snooping for RAM */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+
+# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+	/* Motorola reports IPB should better run at 133 MHz. */
+	*(vu_long *)MPC5XXX_ADDECR |= 1;
+	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
+	addecr = *(vu_long *)MPC5XXX_CDM_CFG;
+	addecr &= ~0x103;
+#  if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
+	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
+	addecr |= 0x01;
+#  else
+	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
+	addecr |= 0x02;
+#  endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
+	*(vu_long *)MPC5XXX_CDM_CFG = addecr;
+# endif	/* CFG_IPBCLK_EQUALS_XLBCLK */
+	/* Configure the XLB Arbiter */
+	*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
+	*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
+
+# if defined(CFG_XLB_PIPELINING)
+	/* Enable piplining */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
+# endif
+#endif	/* CONFIG_MPC5200 */
 }
 
 /*
@@ -170,13 +195,10 @@ int cpu_init_r (void)
 #endif
 	*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
 	*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
+	/* route critical ints to normal ints */
+	*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
 
-#if defined(CONFIG_MPC5200)
-	/* enable timebase */
-	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
 	/* load FEC microcode */
 	loadtask(0, 2);
 #endif