X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmpc512x%2Fcpu_init.c;h=fe6beaf84d28843edf9043a2b088b63af29c3557;hb=52cb4d4fb3487313f5a72ea740f527a4aefaa365;hp=d6949f6bba0ba99a7f61656ba2516f1ce618027a;hpb=d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index d6949f6bba..fe6beaf84d 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * (C) Copyright 2007 DENX Software Engineering
+ * Copyright (C) 2007-2009 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,7 +25,8 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
+#include <asm/io.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -37,39 +38,43 @@ void cpu_init_f (volatile immap_t * im)
 	u32 ips_div;
 
 	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 	/* system performance tweaking */
 
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
 	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
-			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+	out_be32(&im->arbiter.acr,
+		(im->arbiter.acr & ~ACR_PIPE_DEP) |
+		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+	);
 #endif
 
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
 	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
-			   (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+	out_be32(im->arbiter.acr,
+		(im->arbiter.acr & ~(ACR_RPTCNT)) |
+		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+	);
 #endif
 
 	/* RSR - Reset Status Register - clear all status */
 	gd->reset_status = im->reset.rsr;
-	im->reset.rsr = ~(RSR_RES);
+	out_be32(&im->reset.rsr, ~RSR_RES);
 
 	/*
 	 * RMR - Reset Mode Register - enable checkstop reset
 	 */
-	im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+	out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
 
 	/* Set IPS-CSB divider: IPS = 1/2 CSB */
-	ips_div = im->clk.scfr[0];
+	ips_div = in_be32(&im->clk.scfr[0]);
 	ips_div &= ~(SCFR1_IPS_DIV_MASK);
 	ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
-	im->clk.scfr[0] = ips_div;
+	out_be32(&im->clk.scfr[0], ips_div);
 
 	/*
 	 * Enable Time Base/Decrementer
@@ -78,7 +83,7 @@ void cpu_init_f (volatile immap_t * im)
 	 * have udelay() working; if not enabled, usually leads to a hang, like
 	 * during FLASH chip identification etc.
 	 */
-	im->sysconf.spcr |= SPCR_TBEN;
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 }
 
 int cpu_init_r (void)