X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmips%2Fstart.S;h=57db589b94f266e7057ca966a72b6487918cd186;hb=92b8964bed0d1b779d9e26be4e16755b5c635415;hp=074d01d2dde203e88f0a07e54040f39b0c2324ba;hpb=3cac27c1d40b151f295dcfdb514fa928732e4ecf;p=oweals%2Fu-boot.git diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 074d01d2dd..57db589b94 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -22,12 +22,33 @@ * MA 02111-1307 USA */ - #include -#include #include #include + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm #define RVECENT(f,n) \ b f; nop @@ -192,7 +213,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 /* 0xbfc00428 */ .word 0xdc870000 .word 0xfca70000 @@ -203,7 +224,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 #endif /* CONFIG_PURPLE */ .align 4 reset: @@ -213,78 +234,64 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS - - /* CAUSE register */ + /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0 zero, CP0_CAUSE + setup_c0_status_reset + /* Init Timer */ mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Initialize $gp. - */ - bal 1f - nop - .word _gp - 1: - move gp, ra - lw t1, 0(ra) - move gp, t1 - -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. */ - la t9, disable_incaip_wdt - jalr t9 + bal 1f nop -#endif + .word _gp +1: + lw gp, 0(ra) +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* Initialize any external memory. */ - la t9, lowlevel_init - jalr t9 + la t9, lowlevel_init + jalr t9 nop /* Initialize caches... */ - la t9, mips_cache_reset - jalr t9 + la t9, mips_cache_reset + jalr t9 nop /* ... and enable them. */ li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG - +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Set up temporary stack. */ - li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 +#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS + li a0, CONFIG_SYS_INIT_SP_OFFSET + la t9, mips_cache_lock + jalr t9 nop +#endif - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET la sp, 0(t0) la t9, board_init_f - j t9 + jr t9 nop - /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -298,28 +305,37 @@ reset: .globl relocate_code .ent relocate_code relocate_code: - move sp, a0 /* Set new stack pointer */ + move sp, a0 /* Set new stack pointer */ - li t0, CFG_MONITOR_BASE + li t0, CONFIG_SYS_MONITOR_BASE la t3, in_ram lw t2, -12(t3) /* t2 <-- uboot_end_data */ move t1, a2 + move s2, a2 /* s2 <-- destination address */ /* * Fix $gp: * - * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address */ move t6, gp - sub gp, CFG_MONITOR_BASE - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ + sub gp, CONFIG_SYS_MONITOR_BASE + add gp, a2 /* gp now adjusted */ + sub s1, gp, t6 /* s1 <-- relocation offset */ /* * t0 = source address * t1 = target address * t2 = source end address */ + + /* + * Save destination address and size for later usage in flush_cache() + */ + move s0, a1 /* save gd in s0 */ + move a0, t1 /* a0 <-- destination addr */ + sub a1, t2, t0 /* a1 <-- size */ + /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */ @@ -329,19 +345,25 @@ relocate_code: sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b - addu t1, 4 /* delay slot */ + addu t1, 4 /* delay slot */ #endif /* If caches were enabled, we would have to flush them here. */ + /* a0 & a1 are already set up for flush_cache(start, size) */ + la t9, flush_cache + jalr t9 + nop + /* Jump to where we've relocated ourselves. */ - addi t0, a2, in_ram - _start - j t0 + addi t0, s2, in_ram - _start + jr t0 nop - .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */ + .word _gp + .word _GLOBAL_OFFSET_TABLE_ .word uboot_end_data .word uboot_end .word num_got_entries @@ -354,14 +376,16 @@ in_ram: * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) /* t3 <-- num_got_entries */ - lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */ - add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */ + lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ + lw t5, -20(t0) /* t5 <-- _gp */ + sub t4, t5 /* compute offset*/ + add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ addi t4, t4, 8 /* Skipping first two entries. */ li t2, 2 1: lw t1, 0(t4) beqz t1, 2f - add t1, t6 + add t1, s1 sw t1, 0(t4) 2: addi t2, 1 @@ -372,26 +396,26 @@ in_ram: */ lw t1, -12(t0) /* t1 <-- uboot_end_data */ lw t2, -8(t0) /* t2 <-- uboot_end */ - add t1, t6 /* adjust pointers */ - add t2, t6 + add t1, s1 /* adjust pointers */ + add t2, s1 sub t1, 4 -1: addi t1, 4 +1: + addi t1, 4 bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ - move a0, a1 + move a0, s0 /* a0 <-- gd */ la t9, board_init_r - j t9 - move a1, a2 /* delay slot */ + jr t9 + move a1, s2 /* delay slot */ .end relocate_code - /* Exception handlers. */ romReserved: - b romReserved + b romReserved romExcHandle: - b romExcHandle + b romExcHandle