X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmips%2Fcpu.c;h=d5a16047de9500fd6c62815dd3a437d68f3ce636;hb=ee924e00300bd1136589b2d5f8ad1f008df01bd4;hp=0f58d25b892bbcc77ee3436c232d7ecdbadcc89a;hpb=e2ad8426624bac457acc6925b6ff408e9bf20466;p=oweals%2Fu-boot.git

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 0f58d25b89..d5a16047de 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/mipsregs.h>
 #include <asm/cacheops.h>
 #include <asm/reboot.h>
@@ -51,7 +52,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
-	unsigned long lsize = CFG_CACHELINE_SIZE;
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
 	unsigned long addr = start_addr & ~(lsize - 1);
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
@@ -64,6 +65,34 @@ void flush_cache(ulong start_addr, ulong size)
 	}
 }
 
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(Hit_Invalidate_D, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}
+
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
 {
 	write_c0_entrylo0(low0);
@@ -73,3 +102,11 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
 	write_c0_index(index);
 	tlb_write_indexed();
 }
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SOC_AU1X00
+	au1x00_enet_initialize(bis);
+#endif
+	return 0;
+}