X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmips%2Fcache.S;h=1b0efc34a7c3da52d8feb8fac2f90695e59cedfd;hb=e2ad8426624bac457acc6925b6ff408e9bf20466;hp=89ada716c3adbe60b3ed912531fb9d23edfc4abc;hpb=373b16fc0c5ae34d28b9027f809ae3cbf45cdd15;p=oweals%2Fu-boot.git

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 89ada716c3..1b0efc34a7 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -240,14 +240,16 @@ NESTED(mips_cache_reset, 0, ra)
 	 */
 	move	a1, t2
 	move	a2, t4
-	bal	mips_init_icache
+	PTR_LA	t7, mips_init_icache
+	jalr	t7
 
 	/*
 	 * then initialize D-cache.
 	 */
 	move	a1, t3
 	move	a2, t5
-	bal	mips_init_dcache
+	PTR_LA	t7, mips_init_dcache
+	jalr	t7
 
 	jr	RA
 	END(mips_cache_reset)
@@ -282,9 +284,25 @@ LEAF(dcache_disable)
 	and	t0, t0, t1
 	ori	t0, t0, CONF_CM_UNCACHED
 	mtc0	t0, CP0_CONFIG
-	j	ra
+	jr	ra
 	END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+	mfc0	t0, CP0_CONFIG
+	ori	t0, CONF_CM_CMASK
+	xori	t0, CONF_CM_CMASK
+	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	jr	ra
+	END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
@@ -308,7 +326,7 @@ mips_cache_lock:
 	move	a1, a2
 	icacheop(a0,a1,a2,a3,0x1d)
 
-	j	ra
+	jr	ra
 
 	.end	mips_cache_lock
 #endif /* CFG_INIT_RAM_LOCK_MIPS */