X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fmcf52x2%2Fspeed.c;h=c93a5180eb5702f3e84928dc7ad07a6d60eca056;hb=ea393eb1d6a786fc2e895f90abb5f7e7541aef45;hp=f6edd5b6fa81fa2bdaa6946bfc34567f91ecb1fc;hpb=dd08e97361fbc9e79fa5ef1a8acf29273b934b11;p=oweals%2Fu-boot.git

diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index f6edd5b6fa..c93a5180eb 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -39,11 +39,11 @@ int get_clocks (void)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
 
-#ifndef CFG_PLL_BYPASS
+#ifndef CONFIG_SYS_PLL_BYPASS
 
 #ifdef CONFIG_M5249
 	/* Setup the PLL to run at the specified speed */
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
 	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
 #else
 	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
@@ -51,7 +51,7 @@ int get_clocks (void)
 #endif				/* CONFIG_M5249 */
 
 #ifdef CONFIG_M5253
-	pllcr = CFG_PLLCR;
+	pllcr = CONFIG_SYS_PLLCR;
 #endif				/* CONFIG_M5253 */
 
 	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -60,7 +60,7 @@ int get_clocks (void)
 	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
 	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
 	udelay(0x20);		/* Wait for a lock ... */
-#endif				/* #ifndef CFG_PLL_BYPASS */
+#endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
 
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
@@ -76,11 +76,20 @@ int get_clocks (void)
 		;
 #endif
 
-	gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+	gd->cpu_clk = CONFIG_SYS_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;
 #endif
+
+#ifdef CONFIG_FSL_I2C
+	gd->i2c1_clk = gd->bus_clk;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+	gd->i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
 	return (0);
 }