X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Fixp%2Fstart.S;h=196ba5db2eaf760c750b1c4a8b0ac41ea18b1cf6;hb=9eb468da3fd8753de55ab271d6ff5ed7f36d7ea2;hp=09ecc73a00c8a9ce22869ea30eda54dff9b95b39;hpb=f6e20fc6ca5a45316f94743d8b60dce4d9766bc8;p=oweals%2Fu-boot.git

diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S
index 09ecc73a00..196ba5db2e 100644
--- a/cpu/ixp/start.S
+++ b/cpu/ixp/start.S
@@ -140,7 +140,7 @@ reset:
 	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* drain write and fill buffers */
@@ -154,33 +154,34 @@ reset:
 	CPWAIT	r0
 
 	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CFG_EXP_CS0
+	ldr	r1, =CONFIG_SYS_EXP_CS0
 	ldr     r2, =IXP425_EXP_CS0
 	str     r1, [r2]
 
 	/* make sure flash is visible at 0 */
-	ldr 	r2, =IXP425_EXP_CFG0
+#if 0
+	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	orr     r1, r1, #0x80000000
 	str     r1, [r2]
-
-	mov 	r1, #CFG_SDR_CONFIG
+#endif
+	mov	r1, #CONFIG_SYS_SDR_CONFIG
 	ldr     r2, =IXP425_SDR_CONFIG
 	str     r1, [r2]
 
 	/* disable refresh cycles */
-	mov 	r1, #0
+	mov	r1, #0
 	ldr     r3, =IXP425_SDR_REFRESH
 	str	r1, [r3]
 
 	/* send nop command */
-	mov 	r1, #3
+	mov	r1, #3
 	ldr	r4, =IXP425_SDR_IR
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
 
 	/* set SDRAM internal refresh val */
-	ldr	r1, =CFG_SDRAM_REFRESH_CNT
+	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
 	str     r1, [r3]
 	DELAY_FOR 0x4000, r0
 
@@ -198,7 +199,7 @@ reset:
 	bne	111b
 
 	/* set mode register in sdram */
-	mov	r1, #1
+	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
 
@@ -210,7 +211,7 @@ reset:
 	/* copy */
 	mov     r0, #0
 	mov     r4, r0
-	add     r2, r0, #0x40000
+	add     r2, r0, #CONFIG_SYS_MONITOR_LEN
 	mov     r1, #0x10000000
 	mov     r5, r1
 
@@ -225,7 +226,7 @@ reset:
 	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* drain write and fill buffers */
@@ -233,7 +234,7 @@ reset:
 	CPWAIT	r0
 
 	/* move flash to 0x50000000 */
-	ldr 	r2, =IXP425_EXP_CFG0
+	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	bic     r1, r1, #0x80000000
 	str     r1, [r2]
@@ -246,7 +247,7 @@ reset:
 	nop
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* enable I cache */
@@ -260,6 +261,7 @@ reset:
 	orr	r0,r0,#0x13
 	msr	cpsr,r0
 
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
@@ -276,12 +278,13 @@ copy_loop:
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
 	cmp	r0, r2			/* until source end addreee [r2]    */
 	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
@@ -289,14 +292,13 @@ stack_setup:
 
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
-	add	r0, r0, #4		/* start at first byte of bss       */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	bne	clbss_l
+	ble	clbss_l
 
 	ldr	pc, _start_armboot
 
@@ -343,8 +345,8 @@ _start_armboot: .word start_armboot
 	add	r8, sp, #S_PC
 
 	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
+	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
 	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
 
@@ -380,8 +382,8 @@ _start_armboot: .word start_armboot
 
 	.macro get_bad_stack
 	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
@@ -480,13 +482,13 @@ fiq:
 .globl reset_cpu
 
 reset_cpu:
-	ldr 	r1, =0x482e
+	ldr	r1, =0x482e
 	ldr     r2, =IXP425_OSWK
 	str     r1, [r2]
-	ldr 	r1, =0x0fff
+	ldr	r1, =0x0fff
 	ldr     r2, =IXP425_OSWT
 	str     r1, [r2]
-	ldr 	r1, =0x5
+	ldr	r1, =0x5
 	ldr     r2, =IXP425_OSWE
 	str     r1, [r2]
 	b	reset_endless
@@ -495,3 +497,29 @@ reset_cpu:
 reset_endless:
 
 	b	reset_endless
+
+#ifdef CONFIG_USE_IRQ
+
+.LC0:		.word	loops_per_jiffy
+
+/*
+ * 0 <= r0 <= 2000
+ */
+.globl udelay
+udelay:
+	mov	r2,     #0x6800
+	orr	r2, r2, #0x00db
+	mul	r0, r2, r0
+	ldr	r2, .LC0
+	ldr	r2, [r2]		@ max = 0x0fffffff
+	mov	r0, r0, lsr #11		@ max = 0x00003fff
+	mov	r2, r2, lsr #11		@ max = 0x0003ffff
+	mul	r0, r2, r0		@ max = 2^32-1
+	movs	r0, r0, lsr #6
+
+delay_loop:
+	subs	r0, r0, #1
+	bne	delay_loop
+	mov	pc, lr
+
+#endif /* CONFIG_USE_IRQ */