X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Farm926ejs%2Fcpu.c;h=56c6289da6685dd3c174bcda9c97e09cbe3dc16e;hb=ef50d6c06ece74fb17e8d7510e62cad9df8b810d;hp=f57c5a5d89513098a39a86044cf2ab987388bbae;hpb=74f4304ee717d0f4b3a27e7fd4a64944749b8783;p=oweals%2Fu-boot.git

diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index f57c5a5d89..56c6289da6 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm926ejs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
@@ -132,25 +134,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-void icache_enable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_enable(uint32_t cache_bit)
+{
+	uint32_t reg;
+
+	reg = read_p15_c1();	/* get control reg. */
+	cp_delay();
+	write_p15_c1(reg | cache_bit);
+}
+
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_disable(uint32_t cache_bit)
 {
-	ulong reg;
+	uint32_t reg;
 
-	reg = read_p15_c1 ();		/* get control reg. */
-	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	reg = read_p15_c1();
+	cp_delay();
+	write_p15_c1(reg & ~cache_bit);
 }
 
-void icache_disable (void)
+void icache_enable(void)
 {
-	ulong reg;
+	cache_enable(C1_IC);
+}
 
-	reg = read_p15_c1 ();
-	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+void icache_disable(void)
+{
+	cache_disable(C1_IC);
+}
+
+int icache_status(void)
+{
+	return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+	cache_enable(C1_DC);
+}
+
+void dcache_disable(void)
+{
+	cache_disable(C1_DC);
 }
 
-int icache_status (void)
+int dcache_status(void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (read_p15_c1() & C1_DC) != 0;
 }