X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Farm920t%2Finterrupts.c;h=a43a3ed4fe91d0932b60b944eb492f7d5a648de0;hb=2885634d648bdc27fcedb623ddf62475e7684e3b;hp=9ff06c1de78f4c898dbefd9eb594bed702b2eb66;hpb=8bde7f776c77b343aca29b8c7b58464d915ac245;p=oweals%2Fu-boot.git diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index 9ff06c1de7..a43a3ed4fe 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -31,25 +31,8 @@ #include #include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - #include -extern void reset_cpu(ulong addr); -int timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - return (timers->TCNTO4 & 0xffff); -} - #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ void enable_interrupts (void) @@ -178,135 +161,14 @@ void do_fiq (struct pt_regs *pt_regs) void do_irq (struct pt_regs *pt_regs) { +#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) + /* ASSUMED to be a timer interrupt */ + /* Just clear it - count handled in */ + /* integratorap.c */ + *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; +#else printf ("interrupt request\n"); show_regs (pt_regs); bad_mode (); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - /* use PWM Timer 4 because it has no output */ - /* prescaler for Timer 4 is 16 */ - timers->TCFG0 = 0x0f00; - if (timer_load_val == 0) - { - /* - * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 - * (default) and prescaler = 16. Should be 10390 - * @33.25MHz and 15625 @ 50 MHz - */ - timer_load_val = get_PCLK()/(2 * 16 * 100); - } - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - reset_timer_masked (); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - -#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) - tbclk = CFG_HZ; -#else -# error "tbclk not configured" #endif - - return tbclk; }