X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=cpu%2Farm720t%2Fcpu.c;h=60c1aa90b6b97d6f133b62a3e7820df47ff8af03;hb=1a247ba7fa5fb09f56892a09a990f03ce564b3e2;hp=7521fbaf5fcf731dab6209e923bf41623551520f;hpb=a8f88918b1ac95e9ea57ffd01f4c81aeb8a37736;p=oweals%2Fu-boot.git

diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 7521fbaf5f..60c1aa90b6 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -33,7 +33,71 @@
 #include <common.h>
 #include <command.h>
 #include <clps7111.h>
+#include <asm/hardware.h>
 
+int cpu_init (void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 * and we set the CPU-speed to 73 MHz - see start.S for details
+	 */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+	unsigned long i;
+
+	disable_interrupts ();
+
+	/* turn off I-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i &= ~0x1000;
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush I-cache */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+#ifdef CONFIG_ARM7_REVD
+	/* go to high speed */
+	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
+#endif
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
+	disable_interrupts ();
+	/* Nothing more needed */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No cleanup before linux for IntegratorAP/CM720T as yet */
+#else
+#error No cleanup_before_linux() defined for this CPU type
+#endif
+	return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	disable_interrupts ();
+	reset_cpu (0);
+	/*NOTREACHED*/
+	return (0);
+}
+
+/*
+ * Instruction and Data cache enable and disable functions
+ *
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1(void)
 {
@@ -79,62 +143,6 @@ static void cp_delay (void)
 #define C1_ROM_PROT	(1<<9)	/* ROM protection */
 #define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stack if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START   = _armboot_end + \
-				CONFIG_STACKSIZE + \
-				CONFIG_STACKSIZE_IRQ - 4;
-	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
-	_armboot_real_end = FIQ_STACK_START + 4;
-#else
-	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
-#endif
-	return (0);
-}
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 * and we set the CPU-speed to 73 MHz - see start.S for details
-	 */
-
-	unsigned long i;
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-
-#ifdef CONFIG_ARM7_REVD
-	/* go to high speed */
-	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
-#endif
-	return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	extern void reset_cpu (ulong addr);
-
-	disable_interrupts ();
-	reset_cpu (0);
-	/*NOTREACHED*/
-	return (0);
-}
-
 void icache_enable (void)
 {
 	ulong reg;
@@ -180,3 +188,71 @@ int dcache_status (void)
 {
 	return (read_p15_c1 () & C1_IDC) != 0;
 }
+
+#elif defined(CONFIG_S3C4510B)
+
+void icache_enable (void)
+{
+	s32 i;
+
+	/* disable all cache bits */
+	CLR_REG( REG_SYSCFG, 0x3F);
+
+	/* 8KB cache, write enable */
+	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
+
+	/* clear TAG RAM bits */
+	for ( i = 0; i < 256; i++)
+	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
+
+	/* clear SET0 RAM */
+	for(i=0; i < 1024; i++)
+	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
+
+	/* clear SET1 RAM */
+	for(i=0; i < 1024; i++)
+	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
+
+	/* enable cache */
+	SET_REG( REG_SYSCFG, CACHE_ENABLE);
+
+}
+
+void icache_disable (void)
+{
+	/* disable all cache bits */
+	CLR_REG( REG_SYSCFG, 0x3F);
+}
+
+int icache_status (void)
+{
+	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
+}
+
+void dcache_enable (void)
+{
+	/* we don't have seperate instruction/data caches */
+	icache_enable();
+}
+
+void dcache_disable (void)
+{
+	/* we don't have seperate instruction/data caches */
+	icache_disable();
+}
+
+int dcache_status (void)
+{
+	/* we don't have seperate instruction/data caches */
+	return icache_status();
+}
+
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific cache setup for IntegratorAP/CM720T as yet */
+	void icache_enable (void)
+	{
+	}
+#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
+#else
+#error No icache/dcache enable/disable functions defined for this CPU type
+#endif