X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=configs%2Fsocfpga_sr1500_defconfig;h=092347a6df53ecca95dcce19352c0da7433ab58e;hb=22247c63ac4ebed8bbaafe1e717c1de7600a0883;hp=bdc12e4a6af985069272b23e5a3be3b15776556d;hpb=0bb430c8494e26e8d258cf6957cdd39d2ce4f309;p=oweals%2Fu-boot.git

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index bdc12e4a6a..092347a6df 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,10 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_SR1500=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 # CONFIG_USE_BOOTCOMMAND is not set
@@ -15,10 +13,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
@@ -34,23 +32,29 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_MTD_DEVICE=y
 CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
-CONFIG_USE_TINY_PRINTF=y
+# CONFIG_SPL_WDT is not set