X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=configs%2FMPC8349EMDS_SDRAM_defconfig;h=936458a441afd19d34dda863530f4018a4061301;hb=4ba98fa2d4c5e3497e3cb2ca0c73d3fbafa46a59;hp=8465cc6800fe475b79dbbf1a68ff8f0da2f559a5;hpb=21c1502a4a81904706b9883f523ec4a94aba880f;p=oweals%2Fu-boot.git

diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
index 8465cc6800..936458a441 100644
--- a/configs/MPC8349EMDS_SDRAM_defconfig
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
 CONFIG_TARGET_MPC8349EMDS_SDRAM=y
 CONFIG_DDR_MC_CLOCK_MODE_1_1=y
 CONFIG_SYSTEM_PLL_FACTOR_4_1=y
@@ -13,6 +14,81 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y
 CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_TSEC1_MODE_GMII=y
 CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="SDRAM"
+CONFIG_LBLAW2_LENGTH_64_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="SDRAM"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_PORTSIZE_32BIT=y
+CONFIG_BR2_MACHINE_SDRAM=y
+CONFIG_OR2_COLS_9=y
+CONFIG_OR2_ROWS_13=y
+CONFIG_OR2_EAD_EXTRA=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -37,3 +113,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_MPC8XXX_SPI=y
 CONFIG_OF_LIBFDT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y