X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fwandboard%2Fwandboard.c;h=6c1e4ef27dbf967e16e5a1704f3062b5b02bcf24;hb=bf8363931f8bc2a2746f892f154efd170bd5b42e;hp=1075c6589d5d2ecda1a94301ee4d2b6f32eb9434;hpb=21008ad6384170767041f1608975473c5ffa7fc7;p=oweals%2Fu-boot.git diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 1075c6589d..6c1e4ef27d 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -1,12 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. * Copyright (C) 2014 O.S. Systems Software LTDA. * * Author: Fabio Estevam - * - * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -15,20 +15,21 @@ #include #include #include -#include -#include -#include -#include +#include +#include +#include +#include +#include #include +#include #include #include -#include -#include #include #include #include -#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -36,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -47,146 +44,77 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) +#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) +#define REV_DETECTION IMX_GPIO_NR(2, 28) + +/* Speed defined in Kconfig is only applicable when not using DM_I2C. */ +#ifdef CONFIG_DM_I2C +#define I2C1_SPEED_NON_DM 0 +#define I2C2_SPEED_NON_DM 0 +#else +#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED +#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED +#endif + +static bool with_pmic; int dram_init(void) { - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - /* Carrier MicroSD Card Detect */ - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +static iomux_v3_cfg_t const enet_pads[] = { + /* AR8031 PHY Reset */ + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - /* SOM MicroSD Card Detect */ - MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +static iomux_v3_cfg_t const enet_ar8035_power_pads[] = { + /* AR8035 POWER */ + IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8031 PHY Reset */ - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +static iomux_v3_cfg_t const rev_detection_pad[] = { + IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void setup_iomux_uart(void) { - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + SETUP_IOMUX_PADS(uart1_pads); } static void setup_iomux_enet(void) { - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + SETUP_IOMUX_PADS(enet_pads); + + if (with_pmic) { + SETUP_IOMUX_PADS(enet_ar8035_power_pads); + /* enable AR8035 POWER */ + gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER"); + gpio_direction_output(ETH_PHY_AR8035_POWER, 0); + } + /* wait until 3.3V of PHY and clock become stable */ + mdelay(10); /* Reset AR8031 PHY */ + gpio_request(ETH_PHY_RESET, "PHY_RESET"); gpio_direction_output(ETH_PHY_RESET, 0); - udelay(500); + mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); + udelay(100); } -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - /* - * Following map is done: - * (U-boot device node) (Physical Port) - * mmc0 SOM MicroSD - * mmc1 Carrier board MicroSD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gpio_direction_input(USDHC3_CD_GPIO); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[1].max_bus_width = 4; - gpio_direction_input(USDHC1_CD_GPIO); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - -static int mx6_rgmii_rework(struct phy_device *phydev) +static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; + int mask; /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); @@ -194,7 +122,12 @@ static int mx6_rgmii_rework(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; + if (with_pmic) + mask = 0xffe7; /* AR8035 */ + else + mask = 0xffe3; /* AR8031 */ + + val &= mask; val |= 0x18; phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); @@ -209,7 +142,7 @@ static int mx6_rgmii_rework(struct phy_device *phydev) int board_phy_config(struct phy_device *phydev) { - mx6_rgmii_rework(phydev); + ar8031_phy_fixup(phydev); if (phydev->drv->config) phydev->drv->config(phydev); @@ -218,54 +151,100 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -struct i2c_pads_info i2c2_pad_info = { +struct i2c_pads_info mx6q_i2c2_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info mx6dl_i2c2_pad_info = { .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), .gp = IMX_GPIO_NR(4, 13) } }; +struct i2c_pads_info mx6q_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 11) + } +}; + +struct i2c_pads_info mx6dl_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 11) + } +}; + static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */ - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 - | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */ - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */ - - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - - MX6_PAD_SD4_DAT2__GPIO2_IO10 - | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */ - MX6_PAD_SD4_DAT3__GPIO2_IO11 - | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */ + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), + IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ }; static void do_enable_hdmi(struct display_info_t const *dev) @@ -275,16 +254,29 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { +#ifdef CONFIG_DM_I2C + struct udevice *bus, *udev; + int rc; + + rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus); + if (rc) + return rc; + rc = dm_i2c_probe(bus, dev->addr, 0, &udev); + if (rc) + return 0; + return 1; +#else return (0 == i2c_set_bus_num(dev->bus)) && (0 == i2c_probe(dev->addr)); +#endif } static void enable_fwadapt_7wvga(struct display_info_t const *dev) { - imx_iomux_v3_setup_multiple_pads( - fwadapt_7wvga_pads, - ARRAY_SIZE(fwadapt_7wvga_pads)); + SETUP_IOMUX_PADS(fwadapt_7wvga_pads); + gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN"); + gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN"); gpio_direction_output(IMX_GPIO_NR(2, 10), 1); gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } @@ -346,24 +338,50 @@ static void setup_display(void) writel(reg, &mxc_ccm->chsccdr); /* Disable LCD backlight */ - imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20); + SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); + gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN"); gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ -int board_eth_init(bd_t *bis) +int board_early_init_f(void) { - setup_iomux_enet(); + setup_iomux_uart(); +#ifdef CONFIG_SATA + setup_sata(); +#endif - return cpu_eth_init(bis); + return 0; } -int board_early_init_f(void) +#define PMIC_I2C_BUS 2 + +int power_init_board(void) { - setup_iomux_uart(); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif + struct udevice *dev; + int reg, ret; + + puts("PMIC: "); + + ret = pmic_get("pfuze100", &dev); + if (ret < 0) { + printf("pmic_get() ret %d\n", ret); + return 0; + } + + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); + if (reg < 0) { + printf("pmic_reg_read() ret %d\n", reg); + return 0; + } + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + with_pmic = true; + + /* Set VGEN2 to 1.5V and enable */ + reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | (1 << (LDO_EN))); + pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg); return 0; } @@ -385,12 +403,47 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +static bool is_revc1(void) +{ + SETUP_IOMUX_PADS(rev_detection_pad); + gpio_direction_input(REV_DETECTION); + + if (gpio_get_value(REV_DETECTION)) + return true; + else + return false; +} + +static bool is_revd1(void) +{ + if (with_pmic) + return true; + else + return false; +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_mx6dqp()) + env_set("board_rev", "MX6QP"); + else if (is_mx6dq()) + env_set("board_rev", "MX6Q"); + else + env_set("board_rev", "MX6DL"); + + if (is_revd1()) + env_set("board_name", "D1"); + else if (is_revc1()) + env_set("board_name", "C1"); + else + env_set("board_name", "B1"); +#endif + setup_iomux_enet(); return 0; } @@ -399,14 +452,50 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info); +#if defined(CONFIG_VIDEO_IPUV3) + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); + if (is_mx6dq() || is_mx6dqp()) { + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info); + } else { + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info); + } + + setup_display(); +#endif return 0; } int checkboard(void) { - puts("Board: Wandboard\n"); + gpio_request(REV_DETECTION, "REV_DETECT"); + + if (is_revd1()) + puts("Board: Wandboard rev D1\n"); + else if (is_revc1()) + puts("Board: Wandboard rev C1\n"); + else + puts("Board: Wandboard rev B1\n"); return 0; } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_mx6dq()) { + if (!strcmp(name, "imx6q-wandboard-revb1")) + return 0; + } else if (is_mx6dqp()) { + if (!strcmp(name, "imx6qp-wandboard-revd1")) + return 0; + } else if (is_mx6dl() || is_mx6solo()) { + if (!strcmp(name, "imx6dl-wandboard-revb1")) + return 0; + } + + return -EINVAL; +} +#endif