X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fve8313%2Fve8313.c;h=924d87112305b14ffa1a1252a4195b59c8cb9e78;hb=9bc590e5119f38fd822dedb16e3e0e2363f09756;hp=2272ff0c34cb50a59e9602a24b073d45410d29fd;hpb=6050c754b0f06c7b2c867cb9fd279498bc89c393;p=oweals%2Fu-boot.git

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 2272ff0c34..924d871123 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -65,8 +65,14 @@ static long fixed_sdram(void)
 	 */
 	__udelay(50000);
 
-	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	out_be32(&im->ddr.csbnds[0].csbnds,
+		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+			CSBNDS_EA));
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 
 	/* Currently we use only one CS, so disable the other bank. */
 	out_be32(&im->ddr.cs_config[1], 0);
@@ -184,7 +190,6 @@ void pci_init_board(void)
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
-	int warmboot;
 
 	/* Enable all 3 PCI_CLK_OUTPUTs. */
 	setbits_be32(&clk->occr, 0xe0000000);
@@ -198,9 +203,7 @@ void pci_init_board(void)
 	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
 	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
 
-	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
-
-	mpc83xx_pci_init(1, reg, warmboot);
+	mpc83xx_pci_init(1, reg);
 }
 #endif