X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ftqc%2Ftqm85xx%2Ftqm85xx.c;h=e1e75b83abb67e571c9d017ff213035fea3aee1f;hb=ea393eb1d6a786fc2e895f90abb5f7e7541aef45;hp=f1c2e58edd0f02c30346b7c7d6ca672f3b86eb2e;hpb=b77cddc7b52acd4ed78830ac681a398dd3053938;p=oweals%2Fu-boot.git diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f1c2e58edd..e1e75b83ab 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -23,7 +23,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -42,6 +42,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -268,7 +269,7 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -281,9 +282,9 @@ int misc_init_r (void) */ if (flash_info[0].size > 0) { memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CFG_OR1_PRELIM & 0x00007fff); + (CONFIG_SYS_OR1_PRELIM & 0x00007fff); memctl->br1 = gd->bd->bi_flashstart | - (CFG_BR1_PRELIM & 0x00007fff); + (CONFIG_SYS_BR1_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 1 */ @@ -297,9 +298,9 @@ int misc_init_r (void) * If bank 1 is equipped, bank 0 is mapped after bank 1 */ memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CFG_OR0_PRELIM & 0x00007fff); + (CONFIG_SYS_OR0_PRELIM & 0x00007fff); memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CFG_BR0_PRELIM & 0x00007fff); + (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 0 */ @@ -310,26 +311,25 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, 0xffffffff, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); #endif return 0; @@ -341,7 +341,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); @@ -349,7 +349,7 @@ static void upmc_write (u_char addr, uint val) MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ - out_8 ((void __iomem *)CFG_CAN_BASE, 0); + out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); /* normal operation */ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); @@ -358,9 +358,9 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & 0x0f; + ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; get_sys_info (&sys_info); @@ -375,7 +375,7 @@ uint get_lbc_clock (void) return sys_info.freqSystemBus / clkdiv; } - puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); return 0; } @@ -385,8 +385,8 @@ uint get_lbc_clock (void) */ void local_bus_init (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -417,7 +417,7 @@ void local_bus_init (void) gur->lbiuiplldcr1 = dummy; } - lcrr = CFG_LBC_LCRR; + lcrr = CONFIG_SYS_LBC_LCRR; /* * Local Bus Clock > 83.3 MHz. According to timing @@ -457,17 +457,18 @@ void local_bus_init (void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ if (lbc_mhz < 66) { - lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - lbc->ltedr = 0xa4c80000; /* DK: !!! */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ + lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | + LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ } else if (lbc_mhz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -482,7 +483,7 @@ void local_bus_init (void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay (200); /* @@ -501,10 +502,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CFG_OR2_CAN); - out_be32 (&lbc->br2, CFG_BR2_CAN); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); + out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); @@ -536,9 +537,12 @@ void local_bus_init (void) */ static int first_free_busno; -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + +#ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -546,12 +550,12 @@ static struct pci_controller pcie1_hose; static inline void init_pci1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_PCI1 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; /* PORDEVSR[15] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; @@ -576,28 +580,23 @@ static inline void init_pci1(void) /* inbound */ - pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect (hose, (int)&pci->cfg_addr, @@ -610,7 +609,7 @@ static inline void init_pci1(void) first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; @@ -627,22 +626,22 @@ static inline void init_pci1(void) } else { puts ("PCI1: disabled\n"); } -#else /* !(CONFIG_PCI || CONFIG_PCI1) */ +#else /* !CONFIG_PCI1 */ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ -#endif /* CONFIG_PCI || CONFIG_PCI1) */ +#endif /* CONFIG_PCI1 */ } static inline void init_pcie1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -658,27 +657,23 @@ static inline void init_pcie1(void) puts ("\n"); /* inbound */ - pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, @@ -705,31 +700,19 @@ void pci_init_board (void) } #ifdef CONFIG_OF_BOARD_SETUP +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + void ft_board_setup (void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup (blob, bd); - node = fdt_path_offset (blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) - path = fdt_getprop (blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#ifdef CONFIG_PCI1 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif #ifdef CONFIG_PCIE1 - path = fdt_getprop (blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCIE1 */ - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); +#endif } #endif /* CONFIG_OF_BOARD_SETUP */ @@ -742,3 +725,9 @@ int board_early_init_r (void) return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Intialize TSECs first */ + return pci_eth_init(bis); +}