X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fti%2Fevm%2Fevm.c;h=8a3aa0c5bfdad3234d424f0b98e34e58ab3b3791;hb=79f38777947ac7685e2cef8bd977f954ab198c0e;hp=8497aee6de8dd45cc8bb3dfb1e3f55b84497bbf8;hpb=1086c5d6f8541460f0f10e4a302d8aac27e0e6e0;p=oweals%2Fu-boot.git

diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 8497aee6de..8a3aa0c5bf 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -128,8 +128,7 @@ int board_init(void)
  * provides the timing values back to the function that configures
  * the memory.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-		u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
 	int pop_mfr, pop_id;
 
@@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 
 	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
 		/* 256MB DDR */
-		*mcfg = HYNIX_V_MCFG_200(256 << 20);
-		*ctrla = HYNIX_V_ACTIMA_200;
-		*ctrlb = HYNIX_V_ACTIMB_200;
+		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+		timings->ctrla = HYNIX_V_ACTIMA_200;
+		timings->ctrlb = HYNIX_V_ACTIMB_200;
 	} else {
 		/* 128MB DDR */
-		*mcfg = MICRON_V_MCFG_165(128 << 20);
-		*ctrla = MICRON_V_ACTIMA_165;
-		*ctrlb = MICRON_V_ACTIMB_165;
+		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
 	}
-	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-	*mr = MICRON_V_MR_165;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	timings->mr = MICRON_V_MR_165;
 }
 #endif
 
@@ -278,7 +277,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif