X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fti%2Fevm%2Fevm.c;h=8a3aa0c5bfdad3234d424f0b98e34e58ab3b3791;hb=79f38777947ac7685e2cef8bd977f954ab198c0e;hp=30c1c570f16f05a1e490f8c6eb3c9b73d003e918;hpb=fb6440ee9b110b759ef61fd80bbd0df1bbf0f37b;p=oweals%2Fu-boot.git diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 30c1c570f1..8a3aa0c5bf 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, * * Author : @@ -33,9 +33,11 @@ #include #include #include -#include +#include +#include #include #include +#include #include "evm.h" #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 @@ -118,6 +120,41 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. To map the ID values please see + * nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { + /* 256MB DDR */ + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + } else { + /* 128MB DDR */ + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + } + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -195,29 +232,52 @@ static void reset_net_chip(void) rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; } - ret = omap_request_gpio(rst_gpio); + ret = gpio_request(rst_gpio, ""); if (ret < 0) { printf("Unable to get GPIO %d\n", rst_gpio); return ; } /* Configure as output */ - omap_set_gpio_direction(rst_gpio, 0); + gpio_direction_output(rst_gpio, 0); /* Send a pulse on the GPIO pin */ - omap_set_gpio_dataout(rst_gpio, 1); + gpio_set_value(rst_gpio, 1); udelay(1); - omap_set_gpio_dataout(rst_gpio, 0); + gpio_set_value(rst_gpio, 0); udelay(1); - omap_set_gpio_dataout(rst_gpio, 1); + gpio_set_value(rst_gpio, 1); } int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_SMC911X +#define STR_ENV_ETHADDR "ethaddr" + + struct eth_device *dev; + uchar eth_addr[6]; + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("omap3evm: Couldn't get eth device\n"); + rc = -1; + } + } #endif return rc; } #endif /* CONFIG_CMD_NET */ + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0); + return 0; +} +#endif