X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fti%2Fam335x%2Fmux.c;h=6fb2c009ba0faad135a83cd869b6a58bb525d36f;hb=88718be3001055fa2801a44ab10570279b3f2cb7;hp=29929791fcc632852766ab49fd2b8b0de69928a2;hpb=4c25761337570e63e9e2631a81de221e692251e3;p=oweals%2Fu-boot.git diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 29929791fc..6fb2c009ba 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -19,6 +19,7 @@ #include #include #include +#include "../common/board_detect.h" #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { @@ -27,6 +28,36 @@ static struct module_pin_mux uart0_pin_mux[] = { {-1}, }; +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ @@ -35,7 +66,18 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */ + {-1}, +}; + +static struct module_pin_mux mmc0_no_cd_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ {-1}, }; @@ -51,6 +93,10 @@ static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { }; static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ @@ -93,6 +139,11 @@ static struct module_pin_mux gpio0_7_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio0_18_pin_mux[] = { + {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */ + {-1}, +}; + static struct module_pin_mux rgmii1_pin_mux[] = { {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ @@ -130,11 +181,127 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ + {-1}, +}; + +#ifdef CONFIG_MTD_RAW_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ + {-1}, +}; +#elif defined(CONFIG_NOR) +static struct module_pin_mux bone_norcape_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ + {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ + {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ + {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ + {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ + {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ + {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ + {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ + {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ + {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ + {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ + {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ + {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ + {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ + {-1}, +}; +#endif + +static struct module_pin_mux uart3_icev2_pin_mux[] = { + {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */ + {-1}, +}; + +#if defined(CONFIG_NOR_BOOT) +void enable_norboot_pin_mux(void) +{ + configure_module_pin_mux(bone_norcape_pin_mux); +} +#endif + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); } +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} void enable_i2c0_pin_mux(void) { @@ -166,25 +333,41 @@ static unsigned short detect_daughter_board_profile(void) { unsigned short val; +#ifndef CONFIG_DM_I2C if (i2c_probe(I2C_CPLD_ADDR)) return PROFILE_NONE; if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) return PROFILE_NONE; +#else + struct udevice *dev = NULL; + int rc; + rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev); + if (rc) + return PROFILE_NONE; + rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2); + if (rc) + return PROFILE_NONE; +#endif return (1 << (val & PROFILE_MASK)); } -void enable_board_pin_mux(struct am335x_baseboard_id *header) +void enable_board_pin_mux(void) { /* Do board-specific muxes. */ - if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { + if (board_is_bone()) { /* Beaglebone pinmux */ - configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_MTD_RAW_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); - } else if (!strncmp(header->config, "SKU#01", 6)) { +#endif + } else if (board_is_gp_evm()) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); @@ -192,18 +375,53 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); + /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_MTD_RAW_NAND + if (profile & ~(PROFILE_2 | PROFILE_3)) + configure_module_pin_mux(nand_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } - } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { + } else if (board_is_idk()) { + /* Industrial Motor Control (IDK) */ + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_no_cd_pin_mux); + } else if (board_is_evm_sk()) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); + } else if (board_is_bone_lt()) { + if (board_is_bben()) { + /* SanCloud Beaglebone LT Enhanced pinmux */ + configure_module_pin_mux(rgmii1_pin_mux); + } else { + /* Beaglebone LT pinmux */ + configure_module_pin_mux(mii1_pin_mux); + } + /* Beaglebone LT pinmux */ + configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) + configure_module_pin_mux(bone_norcape_pin_mux); +#else + configure_module_pin_mux(mmc1_pin_mux); +#endif + } else if (board_is_pb()) { + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + } else if (board_is_icev2()) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(gpio0_18_pin_mux); + configure_module_pin_mux(uart3_icev2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); } else { - puts("Unknown board, cannot configure pinmux."); - hang(); + /* Unknown board. We might still be able to boot. */ + puts("Bad EEPROM or unknown board, cannot configure pinmux."); } }