X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Frenesas%2Fsh7785lcr%2Flowlevel_init.S;h=24a0ecdf8e2c8a673a5c3a646fc6e6cb7ce79d55;hb=52eb2c79110151b9017a0829c4d44ee7b8e2ca04;hp=50e1789cc5ac1ad0b8414f2215e53412cbfad0b1;hpb=3ec53148eb68ddfb0c3311fb4c06cd2bd0ef3eeb;p=oweals%2Fu-boot.git diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 50e1789cc5..24a0ecdf8e 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -19,33 +19,7 @@ #include #include #include - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm +#include #include @@ -94,22 +68,22 @@ lowlevel_init: wait_timer WAIT_200US /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D write16 PHCR_A, PHCR_D write16 PJCR_A, PJCR_D write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D + write16 PLCR_A, PXCR_D write16 PMCR_A, PMCR_D write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D write8 PEPUPR_A, PEPUPR_D write8 PHPUPR_A, PHPUPR_D @@ -156,6 +130,46 @@ lbsc_29bit: write32 CS6WCR_A, CS_SD_WCR_D lbsc_end: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 64M 0 0 + * 1 0xa4000000 0x04000000 1 16M 0 0 + * 2 0xa6000000 0x08000000 1 16M 0 0 + * 9 0x88000000 0x48000000 1 128M 1 1 + * 10 0x90000000 0x50000000 1 128M 1 1 + * 11 0x98000000 0x58000000 1 128M 1 1 + * 13 0xa8000000 0x48000000 1 128M 0 0 + * 14 0xb0000000 0x50000000 1 128M 0 0 + * 15 0xb8000000 0x58000000 1 128M 0 0 + */ + write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D + write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D + write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D + write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D + write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D + write32 PMB_DATA_USB_A, PMB_DATA_USB_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D + write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D + write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D + write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D + write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D + write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D + write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif write32 CCR_A, CCR_D @@ -164,9 +178,63 @@ lbsc_end: .align 4 -/*------- LBSC -------*/ -MMSELR_A: .long 0xfc400020 -MMSELR_D: .long 0xa5a50002 +/*------- GPIO -------*/ +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 + +PEPUPR_D: .long 0xff +PHPUPR_D: .long 0x00 +PJPUPR_D: .long 0x00 +PKPUPR_D: .long 0x00 +PLPUPR_D: .long 0x00 +PMPUPR_D: .long 0xfc +PNPUPR_D: .long 0x00 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 + +#define GPIO_BASE 0xffe70000 +PACR_A: .long GPIO_BASE + 0x00 +PBCR_A: .long GPIO_BASE + 0x02 +PCCR_A: .long GPIO_BASE + 0x04 +PDCR_A: .long GPIO_BASE + 0x06 +PECR_A: .long GPIO_BASE + 0x08 +PFCR_A: .long GPIO_BASE + 0x0a +PGCR_A: .long GPIO_BASE + 0x0c +PHCR_A: .long GPIO_BASE + 0x0e +PJCR_A: .long GPIO_BASE + 0x10 +PKCR_A: .long GPIO_BASE + 0x12 +PLCR_A: .long GPIO_BASE + 0x14 +PMCR_A: .long GPIO_BASE + 0x16 +PNCR_A: .long GPIO_BASE + 0x18 +PPCR_A: .long GPIO_BASE + 0x1a +PQCR_A: .long GPIO_BASE + 0x1c +PRCR_A: .long GPIO_BASE + 0x1e +PEPUPR_A: .long GPIO_BASE + 0x48 +PHPUPR_A: .long GPIO_BASE + 0x4e +PJPUPR_A: .long GPIO_BASE + 0x50 +PKPUPR_A: .long GPIO_BASE + 0x52 +PLPUPR_A: .long GPIO_BASE + 0x54 +PMPUPR_A: .long GPIO_BASE + 0x56 +PNPUPR_A: .long GPIO_BASE + 0x58 +PPUPR1_A: .long GPIO_BASE + 0x60 +PPUPR2_A: .long GPIO_BASE + 0x62 +P1MSELR_A: .long GPIO_BASE + 0x80 +P2MSELR_A: .long GPIO_BASE + 0x82 + +MMSELR_A: .long 0xfc400020 +#if defined(CONFIG_SH_32BIT) +MMSELR_D: .long 0xa5a50005 +#else +MMSELR_D: .long 0xa5a50002 +#endif /*------- DBSC2 -------*/ #define DBSC2_BASE 0xfe800000 @@ -182,7 +250,7 @@ DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 -DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54 +DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54 DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 DDR_DUMMY_ACCESS_A: .long 0x40000000 @@ -192,7 +260,7 @@ DBSC2_DBTR1_D: .long 0x00040204 DBSC2_DBTR2_D: .long 0x02100308 DBSC2_DBFREQ_D1: .long 0x00000000 DBSC2_DBFREQ_D2: .long 0x00000100 -DBSC2_DBDICODTOCD_D: .long 0x000f0907 +DBSC2_DBDICODTOCD_D:.long 0x000f0907 DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 @@ -212,66 +280,7 @@ DBSC2_DBRFCNT1_D: .long 0x00000926 DBSC2_DBRFCNT2_D: .long 0x00fe00fe DBSC2_DBRFCNT0_D: .long 0x00010000 -WAIT_200US: .long 33333 - -/*------- GPIO -------*/ -#define GPIO_BASE 0xffe70000 -PACR_A: .long GPIO_BASE + 0x00 -PBCR_A: .long GPIO_BASE + 0x02 -PCCR_A: .long GPIO_BASE + 0x04 -PDCR_A: .long GPIO_BASE + 0x06 -PECR_A: .long GPIO_BASE + 0x08 -PFCR_A: .long GPIO_BASE + 0x0a -PGCR_A: .long GPIO_BASE + 0x0c -PHCR_A: .long GPIO_BASE + 0x0e -PJCR_A: .long GPIO_BASE + 0x10 -PKCR_A: .long GPIO_BASE + 0x12 -PLCR_A: .long GPIO_BASE + 0x14 -PMCR_A: .long GPIO_BASE + 0x16 -PNCR_A: .long GPIO_BASE + 0x18 -PPCR_A: .long GPIO_BASE + 0x1a -PQCR_A: .long GPIO_BASE + 0x1c -PRCR_A: .long GPIO_BASE + 0x1e -PEPUPR_A: .long GPIO_BASE + 0x48 -PHPUPR_A: .long GPIO_BASE + 0x4e -PJPUPR_A: .long GPIO_BASE + 0x50 -PKPUPR_A: .long GPIO_BASE + 0x52 -PLPUPR_A: .long GPIO_BASE + 0x54 -PMPUPR_A: .long GPIO_BASE + 0x56 -PNPUPR_A: .long GPIO_BASE + 0x58 -PPUPR1_A: .long GPIO_BASE + 0x60 -PPUPR2_A: .long GPIO_BASE + 0x62 -P1MSELR_A: .long GPIO_BASE + 0x80 -P2MSELR_A: .long GPIO_BASE + 0x82 - -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 - -PEPUPR_D: .long 0xff -PHPUPR_D: .long 0x00 -PJPUPR_D: .long 0x00 -PKPUPR_D: .long 0x00 -PLPUPR_D: .long 0x00 -PMPUPR_D: .long 0xfc -PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 +WAIT_200US: .long 33333 /*------- LBSC -------*/ PASCR_A: .long 0xff000070 @@ -305,7 +314,7 @@ CS4WCR_D: .long 0x00101012 CS_USB_BCR_D: .long 0x11111200 CS_USB_WCR_D: .long 0x00020004 -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ CS_SD_BCR_D: .long 0x00000300 CS_SD_WCR_D: .long 0x00030108 @@ -313,5 +322,55 @@ CS_SD_WCR_D: .long 0x00030108 CS_I2C_BCR_D: .long 0x11111100 CS_I2C_WCR_D: .long 0x00000003 +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) +PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) +PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) +PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) +PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) + +PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) +PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) +PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) +PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) + +PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) +PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) +PMB_DATA_USB_A: .long PMB_DATA_BASE(2) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) +PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) +PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) +PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) +PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) +PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) +PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) + +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 /* check booting mode */ +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + CCR_A: .long 0xff00001c CCR_D: .long 0x0000090b