X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Frenesas%2Flager%2Flager.c;h=36a35a9a9cfbd82e105dd014008f13b1472f3314;hb=c067cef695d8909f2c453eb9fedb718206d906a4;hp=93273b202faa5eed723e8be7311a79d839b23452;hpb=878cd63e02f63f245182a101807186b44e20f116;p=oweals%2Fu-boot.git diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 93273b202f..36a35a9a9c 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -1,25 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 /* * board/renesas/lager/lager.c * This file is lager board support. * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013 Nobuhiro Iwamatsu - * - * SPDX-License-Identifier: GPL-2.0 */ #include +#include +#include +#include +#include +#include #include #include +#include +#include #include #include #include -#include +#include +#include +#include #include #include #include +#include +#include +#include #include #include +#include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,108 +62,60 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C -#define SCIF0_MSTP721 (1 << 21) +#define TMU0_MSTP125 BIT(25) -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 -#define ETHER_MSTP813 (1 << 13) - -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 int board_early_init_f(void) { - /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 and SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); return 0; } -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -} +#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */ -DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7790_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REF_CLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_GP_5_31, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_31, 1); - udelay(1); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_ETHER - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - return ret; + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); + return 0; +} -#endif +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); - return ret; + return 0; } -/* lager has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +/* KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { @@ -163,24 +127,40 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int dram_init(void) +void reset_cpu(ulong addr) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + struct udevice *dev; + const u8 pmic_bus = 2; + const u8 pmic_addr = 0x58; + u8 data; + int ret; - return 0; -} + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); -const struct rmobile_sysinfo sysinfo = { - CONFIG_RMOBILE_BOARD_STRING -}; + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); -void reset_cpu(ulong addr) + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); +} + +enum env_location env_get_location(enum env_operation op, int prio) { - u8 val; + const u32 load_magic = 0xb33fc0de; + + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; - i2c_set_bus_num(3); /* PowerIC connected to ch3 */ - i2c_init(400000, 0); - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + return ENVL_SPI_FLASH; }