X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fnvidia%2Fcommon%2Fboard.c;h=e650feda481b924d80995739dbcfa56b78b44b14;hb=e97f9d817e600cd6f43d1d0da76f5787e33a5c56;hp=d1a7f3a21cc6d050657b789e6f67d0c49bb94362;hpb=00a2749d7be5b0e6cb6435187ec8fea600b44627;p=oweals%2Fu-boot.git diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d1a7f3a21c..e650feda48 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -2,62 +2,52 @@ * (C) Copyright 2010,2011 * NVIDIA Corporation * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#include -#include - -#include -#include #include -#include +#ifdef CONFIG_LCD +#include +#endif +#include #include -#include #include -#include -#include -#include +#ifdef CONFIG_PWM_TEGRA +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TEGRA_CLOCK_SCALING +#include +#endif +#ifdef CONFIG_USB_EHCI_TEGRA +#include #include +#include +#endif +#ifdef CONFIG_TEGRA_MMC +#include +#include +#endif #include -#include "board.h" +#include #include "emc.h" DECLARE_GLOBAL_DATA_PTR; -const struct tegra20_sysinfo sysinfo = { - CONFIG_TEGRA20_BOARD_STRING +const struct tegra_sysinfo sysinfo = { + CONFIG_TEGRA_BOARD_STRING }; -/* - * Routine: timer_init - * Description: init the timestamp and lastinc value - */ -int timer_init(void) -{ - return 0; -} - void __pin_mux_usb(void) { } @@ -70,6 +60,26 @@ void __pin_mux_spi(void) void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); +void __gpio_early_init_uart(void) +{ +} + +void gpio_early_init_uart(void) +__attribute__((weak, alias("__gpio_early_init_uart"))); + +void __pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); +} + +void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); + +void __pin_mux_display(void) +{ +} + +void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display"))); + /* * Routine: power_det_init * Description: turn off power detects @@ -77,7 +87,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); static void power_det_init(void) { #if defined(CONFIG_TEGRA20) - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; /* turn off power detects */ writel(0, &pmc->pmc_pwr_det_latch); @@ -97,19 +107,25 @@ int board_init(void) clock_init(); clock_verify(); -#ifdef CONFIG_SPI_UART_SWITCH - gpio_config_uart(); -#endif -#ifdef CONFIG_TEGRA_SPI +#ifdef CONFIG_FDT_SPI pin_mux_spi(); spi_init(); #endif + +#ifdef CONFIG_PWM_TEGRA + if (pwm_init(gd->fdt_blob)) + debug("%s: Failed to init pwm\n", __func__); +#endif +#ifdef CONFIG_LCD + pin_mux_display(); + tegra_lcd_check_next_stage(gd->fdt_blob, 0); +#endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); power_det_init(); -#ifdef CONFIG_TEGRA_I2C +#ifdef CONFIG_SYS_I2C_TEGRA #ifndef CONFIG_SYS_I2C_INIT_BOARD #error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards" #endif @@ -123,14 +139,25 @@ int board_init(void) debug("Memory controller init failed: %d\n", err); # endif # endif /* CONFIG_TEGRA_PMU */ -#endif /* CONFIG_TEGRA_I2C */ +#endif /* CONFIG_SYS_I2C_TEGRA */ #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); - board_usb_init(gd->fdt_blob); + usb_process_devicetree(gd->fdt_blob); +#endif + +#ifdef CONFIG_LCD + tegra_lcd_check_next_stage(gd->fdt_blob, 0); +#endif + +#ifdef CONFIG_TEGRA_NAND + pin_mux_nand(); #endif -#ifdef CONFIG_TEGRA20_LP0 +#ifdef CONFIG_TEGRA_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif @@ -147,15 +174,77 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { +#if !defined(CONFIG_TEGRA20) + pinmux_init(); +#endif board_init_uart_f(); /* Initialize periph GPIOs */ gpio_early_init(); -#ifdef CONFIG_SPI_UART_SWITCH gpio_early_init_uart(); -#else - gpio_config_uart(); +#ifdef CONFIG_LCD + tegra_lcd_early_init(gd->fdt_blob); #endif + return 0; } #endif /* EARLY_INIT */ + +int board_late_init(void) +{ +#ifdef CONFIG_LCD + /* Make sure we finish initing the LCD */ + tegra_lcd_check_next_stage(gd->fdt_blob, 1); +#endif + return 0; +} + +#if defined(CONFIG_TEGRA_MMC) +void __pin_mux_mmc(void) +{ +} + +void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("%s called\n", __func__); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + debug("%s: init MMC\n", __func__); + tegra_mmc_init(); + + return 0; +} + +void pad_init_mmc(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + enum periph_id id = host->mmc_id; + u32 val; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} +#endif /* MMC */