X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fnetta2%2Fnetta2.c;h=ff713d9bba963841afda8e3b67c8ee361a00e8c9;hb=07eb5f9ce70cbed40d0bb2799430a0978e054ef2;hp=3ca7bd3c8677e86321d68a417a2e56ea2b17ee02;hpb=951a954b77ef30df1f5c1b7b9b4312e783b2cbb4;p=oweals%2Fu-boot.git

diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
index 3ca7bd3c86..ff713d9bba 100644
--- a/board/netta2/netta2.c
+++ b/board/netta2/netta2.c
@@ -354,7 +354,7 @@ static const uint nandcs_table[0x40] = {
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
 
 /* 8 */
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -402,9 +402,9 @@ void check_ram(unsigned int addr, unsigned int size)
 	}
 }
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -420,10 +420,10 @@ long int initdram(int board_type)
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -486,13 +486,13 @@ void reset_phys(void)
 	mii_init();
 
 	for (phyno = 0; phyno < 32; ++phyno) {
-		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
+		fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
 		if (v == 0xFFFF)
 			continue;
-		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
 		udelay(10000);
-		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
-				PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+				BMCR_RESET | BMCR_ANENABLE);
 		udelay(10000);
 	}
 }
@@ -544,7 +544,7 @@ void reset_phys(void)
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -595,22 +595,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
-#include <linux/mtd/nand_legacy.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	unsigned long totlen;
-
-	totlen = nand_probe(CFG_NAND_BASE);
-	printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
 #ifdef CONFIG_HW_WATCHDOG
 
 void hw_watchdog_reset(void)
@@ -620,21 +604,7 @@ void hw_watchdog_reset(void)
 
 #endif
 
-#ifdef CONFIG_SHOW_ACTIVITY
-
-/* called from timer interrupt every 1/CFG_HZ sec */
-void board_show_activity(ulong timestamp)
-{
-}
-
-/* called when looping */
-void show_activity(int arg)
-{
-}
-
-#endif
-
-#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 int overwrite_console(void)
 {
 	/* printf("overwrite_console called\n"); */
@@ -659,10 +629,10 @@ int last_stage_init(void)
 
 #if CONFIG_NETTA2_VERSION == 2
 	/* assert peripheral reset */
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
 	for (i = 0; i < 10; i++)
 		udelay(1000);
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
 #endif
 	reset_phys();