X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fnetstal%2Fhcu5%2Fsdram.c;h=0546cd726d15b834469d37385eb737410fd3ca3f;hb=1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67;hp=5435de1249c82c56368bca3890906eca85848bad;hpb=40dcd6aa75ef95b490f342695f970910b82e392e;p=oweals%2Fu-boot.git diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 5435de1249..0546cd726d 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -34,33 +34,11 @@ #include #include #include +#include #include void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); - -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -70,8 +48,6 @@ void dflush(void); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); - void board_add_ram_info(int use_default) { PPC4xx_SYS_INFO board_cfg; @@ -95,7 +71,7 @@ void board_add_ram_info(int use_default) } get_sys_info(&board_cfg); - printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000); + printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000); mfsdram(DDR0_03, val); val = DDR0_03_CASLAT_DECODE(val); @@ -113,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(SDRAM0_CFGADDR, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(SDRAM0_CFGDATA); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ @@ -146,7 +122,7 @@ void sdram_panic(const char *reason) } #ifdef CONFIG_DDR_ECC -static void blank_string(int size) +void blank_string(int size) { int i; @@ -165,30 +141,36 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) u32 val; char str[] = "ECC generation -"; #if defined(CONFIG_PRAM) - u32 *magic; - - /* Check whether vxWorks is using EDR logging, if yes zero */ - /* also PostMortem and user reserved memory */ - magic = (u32 *)in_be32((u32 *)(start_address + num_bytes - - (CONFIG_PRAM*1024) + sizeof(u32))); - - debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__, - CONFIG_PRAM, - start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32), - magic, in_be32(magic)); - if (in_be32(magic) == 0xbeefbabe) - num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; + u32 *magicPtr; + u32 magic; + + if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) { + /* only if no external debugger is alive! + * Check whether vxWorks is using EDR logging, if yes zero + * also PostMortem and user reserved memory + */ + magicPtr = (u32 *)(start_address + num_bytes - + (CONFIG_PRAM*1024) + sizeof(u32)); + magic = in_be32(magicPtr); + debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n", + __FUNCTION__, CONFIG_PRAM, + magicPtr, magic); + if (magic == 0xbeefbabe) { + printf("%s: preserving at %p\n", __FUNCTION__, magicPtr); + num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; + } + } #endif sync(); - eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ @@ -200,7 +182,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) * If not done, then we could get an interrupt later on when * exceptions are enabled. */ - mtspr(mcsr, mfspr(mcsr)); + mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); @@ -217,7 +199,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned int dram_size = 0; @@ -281,20 +263,20 @@ long int initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ - remove_tlb(CFG_SDRAM_BASE, 256 << 20); + remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual * address with cache enabled. This is done for fast ECC generation. */ - program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0); #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ - program_ecc(CFG_DDR_CACHED_ADDR, dram_size); + program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size); #endif return (dram_size);