X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fkorat%2Fkorat.c;h=8328ba326dbd3ca2a9ea7960627ba4f57e0b5836;hb=80522dc8369a89938369fbcee572e662373bc9a3;hp=90fd0a753212d1b30dffa23ea839e322a38dc29c;hpb=f58934551e052db5a1f33f53dcc9cbf6fcb72910;p=oweals%2Fu-boot.git diff --git a/board/korat/korat.c b/board/korat/korat.c index 90fd0a7532..8328ba326d 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -1,13 +1,13 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Larry Johnson, lrj@acm.org * - * (C) Copyright 2006-2008 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,25 +26,61 @@ */ #include +#include #include +#include #include +#include #include -#include #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); +#if defined(CONFIG_KORAT_PERMANENT) +void korat_buzzer(int const on) +{ + if (on) { + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80); + } else { + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80); + } +} +#endif + int board_early_init_f(void) { - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; + uint32_t sdr0_pfc1, sdr0_pfc2; + uint32_t reg; int eth; +#if defined(CONFIG_KORAT_PERMANENT) + unsigned mscount; + + extern void korat_branch_absolute(uint32_t addr); + + for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { + udelay(1000); + if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { + /* This call does not return. */ + korat_branch_absolute( + CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); + } + } + korat_buzzer(1); + while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) + udelay(1000); + + korat_buzzer(0); +#endif + mtdcr(ebccfga, xbcfg); mtdcr(ebccfgd, 0xb8400000); @@ -75,34 +111,45 @@ int board_early_init_f(void) mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ - /* take sim card reader and CF controller out of reset */ - out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80); + /* + * Take sim card reader and CF controller out of reset. Also enable PHY + * auto-detect until board-specific PHY resets are available. + */ + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. */ for (eth = 0; eth < 2; ++eth) { - if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) { + if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ - out_8((u8 *) CFG_CPLD_BASE + 0x06, - in_8((u8 *) CFG_CPLD_BASE + 0x06) | + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x06 << (4 * eth)); } else { /* SFP module present: configure PHY for fiber and enable output */ - gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1); - gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); + gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); } } /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ - gpio_write_bit(CFG_GPIO_PHY0_EN, 1); - gpio_write_bit(CFG_GPIO_PHY1_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); - /* select Ethernet pins */ + /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ + udelay(1000); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); + + /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; +#ifdef CONFIG_I2C_MULTI_BUS + sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); +#endif mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; @@ -116,6 +163,58 @@ int board_early_init_f(void) return 0; } +/* + * The boot flash on CS0 normally has its write-enable pin disabled, and so will + * not respond to CFI commands. This routine therefore fills in the flash + * information for the boot flash. (The flash at CS1 operates normally.) + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + uint32_t addr; + int i; + + if (1 != banknum) + return 0; + + info->size = CONFIG_SYS_FLASH0_SIZE; + info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000; + info->flash_id = 0x01000000; + info->portwidth = 2; + info->chipwidth = 2; + info->buffer_size = 32; + info->erase_blk_tout = 16384; + info->write_tout = 2; + info->buffer_write_tout = 5; + info->vendor = 2; + info->cmd_reset = 0x00F0; + info->interface = 2; + info->legacy_unlock = 0; + info->manufacturer_id = 1; + info->device_id = 0x007E; + +#if CONFIG_SYS_FLASH0_SIZE == 0x01000000 + info->device_id2 = 0x2101; +#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 + info->device_id2 = 0x2301; +#else +#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE +#endif + + info->ext_addr = 0x0040; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0055; + info->addr_unlock1 = 0x00000555; + info->addr_unlock2 = 0x000002AA; + info->name = "CFI conformant"; + for (i = 0, addr = -info->size; + i < info->sector_count; + ++i, addr += 0x20000) { + info->start[i] = addr; + info->protect[i] = 0x00; + } + return 1; +} + static int man_data_read(unsigned int addr) { /* @@ -189,12 +288,20 @@ static void set_serial_number(void) * If the environmental variable "serial#" is not set, try to set it * from the manufacturer's information serial EEPROM. */ - char s[MAN_SERIAL_NO_LENGTH + 1]; + char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2]; - if (0 == getenv("serial#") && - 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD, - MAN_SERIAL_NO_LENGTH)) - setenv("serial#", s); + if (getenv("serial#")) + return; + + if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH)) + return; + + s[MAN_INFO_LENGTH] = '-'; + if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD, + MAN_MAC_ADDR_LENGTH)) + return; + + setenv("serial#", s); } static void set_mac_addresses(void) @@ -204,45 +311,59 @@ static void set_mac_addresses(void) * set, try to set them from the manufacturer's information serial * EEPROM. */ - char s[MAN_MAC_ADDR_LENGTH + 1]; + +#if MAN_MAC_ADDR_LENGTH % 2 != 0 +#error MAN_MAC_ADDR_LENGTH must be an even number +#endif + + char s[(3 * MAN_MAC_ADDR_LENGTH) / 2]; + char *src; + char *dst; if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) return; - if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD, - MAN_MAC_ADDR_LENGTH)) + if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1, + MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH)) return; + for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) { + *dst++ = *src++; + *dst++ = *src++; + *dst++ = ':'; + } if (0 == getenv("ethaddr")) setenv("ethaddr", s); if (0 == getenv("eth1addr")) { - ++s[MAN_MAC_ADDR_LENGTH - 1]; + ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2]; setenv("eth1addr", s); } } int misc_init_r(void) { - uint pbcr; - int size_val = 0; - u32 reg; + uint32_t pbcr; + int size_val; + uint32_t reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; - char *act = getenv("usbact"); + uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; + char const *const act = getenv("usbact"); + char const *const usbcf = getenv("korat_usbcf"); - /* Re-do flash sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + /* + * Re-do FLASH1 sizing and adjust flash start and offset. + */ + gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb0cr); + mtdcr(ebccfga, pb1cr); pbcr = mfdcr(ebccfgd); - size_val = ffs(gd->bd->bi_flashsize) - 21; + size_val = ffs(flash1_size) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); + mtdcr(ebccfga, pb1cr); mtdcr(ebccfgd, pbcr); /* @@ -250,18 +371,61 @@ int misc_init_r(void) */ flash_get_size(gd->bd->bi_flashstart, 0); - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, - &flash_info[0]); + /* + * Re-do FLASH1 sizing and adjust flash offset to reserve space for + * environment + */ + gd->bd->bi_flashoffset = + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; + + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb1cr); + mtdcr(ebccfgd, pbcr); + /* Monitor protection ON by default */ +#if defined(CONFIG_KORAT_PERMANENT) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, + flash_info + 1); +#else + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, + flash_info); +#endif /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + flash_info); + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, + flash_info); /* * USB suff... */ + /* + * Select the USB controller on the 440EPx ("ppc") or on the PCI bus + * ("pci") for the CompactFlash. + */ + if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) { + /* + * If environment variable "usbcf" is defined and set to "ppc", + * then connect the CompactFlash controller to the PowerPC USB + * port. + */ + printf("Attaching CompactFalsh controller to PPC USB\n"); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10); + } else { + if (usbcf != NULL && (strcmp(usbcf, "pci") != 0)) + printf("Warning: \"korat_usbcf\" is not set to a legal " + "value (\"ppc\" or \"pci\")\n"); + + printf("Attaching CompactFalsh controller to PCI USB\n"); + } if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -393,71 +557,48 @@ int misc_init_r(void) set_serial_number(); set_mac_addresses(); + gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1); + return 0; } int checkboard(void) { char const *const s = getenv("serial#"); - u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); + u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0); printf("Board: Korat, Rev. %X", rev); - if (s != NULL) + if (s) printf(", serial# %s", s); - printf(", Ethernet PHY 0: "); - if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL)) + printf(".\n Ethernet PHY 0: "); + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL)) printf("fiber"); else printf("copper"); printf(", PHY 1: "); - if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL)) + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL)) printf("fiber"); else printf("copper"); printf(".\n"); - return (0); +#if defined(CONFIG_KORAT_PERMANENT) + printf(" Executing permanent copy of U-Boot.\n"); +#endif + return 0; } -#if defined(CFG_DRAM_TEST) -int testdram(void) +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. + */ +void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - /* TODO: find correct size of SDRAM */ - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) - printf("%3d MB\r", k / 1024); - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); } -#endif /* defined(CFG_DRAM_TEST) */ +#endif /* * pci_pre_init @@ -509,6 +650,10 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#if defined(CONFIG_PCI_PNP) + hose->fixup_irq = korat_pci_fixup_irq; +#endif + return 1; } #endif /* defined(CONFIG_PCI) */ @@ -520,7 +665,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /* @@ -529,23 +674,26 @@ void pci_target_init(struct pci_controller *hose) /* * PowerPC440EPX PCI Master configuration. * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF + * PLB address 0x80000000-0xBFFFFFFF + * ==> PCI address 0x80000000-0xBFFFFFFF * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, + CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, + CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, + CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -561,8 +709,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -581,9 +729,9 @@ void pci_target_init(struct pci_controller *hose) */ pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -631,3 +779,24 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 1; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */