X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fkeymile%2Fkm_arm%2Fkm_arm.c;h=5620737bf06f52cbccf8ead975529b77706f2202;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=ca33aaec534935bc2357652816a8532a73210055;hpb=688d8f33f27ea596efb6632388ee60360996eed0;p=oweals%2Fu-boot.git diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ca33aaec53..5620737bf0 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -9,23 +9,7 @@ * (C) Copyright 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -33,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -53,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MASK_RBI_DEFECT_16 0x01 /* Multi-Purpose Pins Functionality configuration */ -u32 kwmpp_config[] = { +static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, @@ -62,7 +47,7 @@ u32 kwmpp_config[] = { MPP5_NF_IO7, MPP6_SYSRST_OUTn, MPP7_PEX_RST_OUTn, -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ #endif @@ -113,7 +98,7 @@ u32 kwmpp_config[] = { 0 }; -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -133,10 +118,10 @@ int startup_allowed(void) } #endif -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { @@ -159,7 +144,7 @@ int ethernet_present(void) } #endif -int initialize_unit_leds(void) +static int initialize_unit_leds(void) { /* * Init the unit LEDs per default they all are @@ -180,7 +165,7 @@ int initialize_unit_leds(void) } #if defined(CONFIG_BOOTCOUNT_LIMIT) -void set_bootcount_addr(void) +static void set_bootcount_addr(void) { uchar buf[32]; unsigned int bootcountaddr; @@ -192,16 +177,7 @@ void set_bootcount_addr(void) int misc_init_r(void) { - char *str; - int mach_type; - - str = getenv("mach_type"); - if (str != NULL) { - mach_type = simple_strtoul(str, NULL, 10); - printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); - gd->bd->bi_arch_number = mach_type; - } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -242,120 +218,99 @@ int misc_init_r(void) int board_early_init_f(void) { +#if defined(CONFIG_SYS_I2C_SOFT) u32 tmp; - kirkwood_mpp_conf(kwmpp_config); + /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + /* adjust SDRAM size for bank 0 */ + kw_sdram_size_adjust(0); + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; /* - * The FLASH_GPIO_PIN switches between using a + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); -#if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ +#if defined(CONFIG_SYS_I2C_SOFT) + /* + * Reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f + */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); -#endif - return 0; -} -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; +#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); +#endif return 0; } -#if defined(CONFIG_CMD_SF) -int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int board_late_init(void) { - u32 tmp; - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "off") == 0)) { - printf("SPI FLASH disabled, NAND enabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - } else if ((strcmp(argv[1], "on") == 0)) { - printf("SPI FLASH enabled, NAND disabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); - } else { - return cmd_usage(cmdtp); +#if defined(CONFIG_KMCOGE5UN) +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); + + /* if pin 1 do full erase */ + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); } +#endif +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif return 0; } -U_BOOT_CMD( - spitoggle, 2, 0, do_spi_toggle, - "En-/disable SPI FLASH access", - " - Enable (on) or disable (off) SPI FLASH access\n" - ); -#endif - -int dram_init(void) +int board_spi_claim_bus(struct spi_slave *slave) { - /* dram_init must store complete ramsize in gd->ram_size */ - /* Fix this */ - gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), - kw_sdram_bs(0)); + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); + return 0; } -void dram_init_banksize(void) +void board_spi_release_bus(struct spi_slave *slave) { - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), - kw_sdram_bs(i)); - } + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); } -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)) -#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1) /* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -367,20 +322,85 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } +#elif defined(CONFIG_KM_PIGGY4_88E6352) + +#include + +#if defined(CONFIG_KM_NUSA) +struct mv88e_sw_reg extsw_conf[] = { + /* + * port 0, PIGGY4, autoneg + * first the fix for the 1000Mbits Autoneg, this is from + * a Marvell errata, the regs are undocumented + */ + { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, + { PHY(0), PHY_STATUS, AN1000FIX }, + { PHY(0), PHY_PAGE, 0 }, + /* now the real port and phy configuration */ + { PORT(0), PORT_PHY, NO_SPEED_FOR }, + { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(0), PHY_1000_CTRL, NO_ADV }, + { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, + { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | + FULL_DUPLEX }, + /* port 1, unused */ + { PORT(1), PORT_CTRL, PORT_DIS }, + { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 2, unused */ + { PORT(2), PORT_CTRL, PORT_DIS }, + { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 3, unused */ + { PORT(3), PORT_CTRL, PORT_DIS }, + { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 4, ICNEV, SerDes, SGMII */ + { PORT(4), PORT_STATUS, NO_PHY_DETECT }, + { PORT(4), PORT_PHY, SPEED_1000_FOR }, + { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 5, CPU_RGMII */ + { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | + FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | + FULL_DPX_FOR | SPEED_1000_FOR }, + { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* port 6, unused, this port has no phy */ + { PORT(6), PORT_CTRL, PORT_DIS }, +}; +#else +struct mv88e_sw_reg extsw_conf[] = {}; +#endif + +void reset_phy(void) +{ +#if defined(CONFIG_KM_MVEXTSW_ADDR) + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, + ARRAY_SIZE(extsw_conf)); + mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); +#endif +} + #else /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) @@ -404,59 +424,7 @@ int hush_init_var(void) } #endif -#if defined(CONFIG_BOOTCOUNT_LIMIT) -const ulong patterns[] = { 0x00000000, - 0xFFFFFFFF, - 0xFF00FF00, - 0x0F0F0F0F, - 0xF0F0F0F0}; -const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); -const ulong OFFS_PATTERN = 3; -const ulong REPEAT_PATTERN = 1000; - -void bootcount_store(ulong a) -{ - volatile ulong *save_addr; - volatile ulong size = 0; - int i; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; - } - save_addr = (ulong*)(size - BOOTCOUNT_ADDR); - writel(a, save_addr); - writel(BOOTCOUNT_MAGIC, &save_addr[1]); - - for (i = 0; i < REPEAT_PATTERN; i++) - writel(patterns[i % NBR_OF_PATTERNS], - &save_addr[i+OFFS_PATTERN]); - -} - -ulong bootcount_load(void) -{ - volatile ulong *save_addr; - volatile ulong size = 0; - ulong counter = 0; - int i, tmp; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; - } - save_addr = (ulong*)(size - BOOTCOUNT_ADDR); - - counter = readl(&save_addr[0]); - - /* Is the counter reliable, check in the big pattern for bit errors */ - for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { - tmp = readl(&save_addr[i+OFFS_PATTERN]); - if (tmp != patterns[i % NBR_OF_PATTERNS]) - counter = 0; - } - return counter; -} -#endif - -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) void set_sda(int state) { I2C_ACTIVE; @@ -487,18 +455,22 @@ int get_scl(void) int post_hotkeys_pressed(void) { +#if defined(CONFIG_KM_COGE5UN) + return kw_gpio_get_value(KM_POST_EN_L); +#else return !kw_gpio_get_value(KM_POST_EN_L); +#endif } ulong post_word_load(void) { - volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); + void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); return in_le32(addr); } void post_word_store(ulong value) { - volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); + void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); out_le32(addr, value); }