X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fintegratorcp%2Flowlevel_init.S;h=18f7d2eaebe7ef796f817a14032cb2bd79bf0388;hb=d4fc6012fd0a5c211b825691f44b06f8032c0551;hp=e679215f3f221879c2f1410579b844521613e53a;hpb=87cb6862b94e342d6c99467e0dbb0d4f625cc7ef;p=oweals%2Fu-boot.git

diff --git a/board/integratorcp/lowlevel_init.S b/board/integratorcp/lowlevel_init.S
index e679215f3f..18f7d2eaeb 100644
--- a/board/integratorcp/lowlevel_init.S
+++ b/board/integratorcp/lowlevel_init.S
@@ -63,22 +63,22 @@ lowlevel_init:
 	orr	r2,r2,#CMMASK_INIT_102
 #else
 
-#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
-    !defined (CONFIG_CM940T)
-    /* CMxx6 code */
+#if	!defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+	!defined (CONFIG_CM940T)
+	/* CMxx6 code	*/
 
 #ifdef	CONFIG_CM_MULTIPLE_SSRAM
-	/* set simple mapping		  */
+	/* set simple mapping			*/
 	and	r2,r2,#CMMASK_MAP_SIMPLE
-#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
 
 #ifdef	CONFIG_CM_TCRAM
-	/* disable TCRAM		  */
+	/* disable TCRAM			*/
 	and	r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM	  */
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
 
 #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
-	    defined (CONFIG_CM1136JF_S)
+			defined (CONFIG_CM1136JF_S)
 
 	and	r2,r2,#CMMASK_LE
 
@@ -90,7 +90,7 @@ lowlevel_init:
 
 #endif /* ARM102xxE value */
 
-	/* read CM_INIT	   */
+	/* read CM_INIT		 */
 	mov	r0, #CM_BASE
 	ldr	r1, [r0, #OS_INIT]
 	/* check against desired bit setting */
@@ -121,33 +121,33 @@ init_reg_OK:
 #ifdef	CONFIG_CM_SPD_DETECT
 	/* Fast memory is available for the DRAM data
 	 * - ensure it has been transferred, then summarize the data
-	 *   into a CM register
+	 *	 into a CM register
 	 */
 .globl dram_query
 dram_query:
 	stmfd	r13!,{r4-r6,lr}
-	/* set up SDRAM info				  */
+	/* set up SDRAM info					*/
 	/* - based on example code from the CM User Guide */
 	mov	r0, #CM_BASE
 
 readspdbit:
 	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register */
-	and	r1, r1, #0x20		/* mask SPD bit (5)	   */
-	cmp	r1, #0x20		/* test if set		   */
+	and	r1, r1, #0x20		/* mask SPD bit (5)		 */
+	cmp	r1, #0x20		/* test if set			 */
 	bne	readspdbit
 
 setupsdram:
-	add	r0, r0, #OS_SPD		/* address the copy of the SDP data */
-	ldrb	r1, [r0, #3]		/* number of row address lines	    */
-	ldrb	r2, [r0, #4]		/* number of column address lines   */
-	ldrb	r3, [r0, #5]		/* number of banks		    */
-	ldrb	r4, [r0, #31]		/* module bank density		    */
-	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)  */
-	mov	r5, r5, ASL#2		/* size in MB			    */
-	mov	r0, #CM_BASE		/* reload for later code	    */
-	cmp	r5, #0x10		/* is it 16MB?			    */
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
 	bne	not16
-	mov	r6, #0x2		/* store size and CAS latency of 2  */
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
 	b	writesize
 
 not16:
@@ -198,17 +198,17 @@ cm_remap:
 	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
 	str	r1, [r0, #OS_CTRL]
 
-	/* Now 0x00000000 is writeable, replace the vectors  */
-	ldr	r0, =_start	/* r0 <- start of vectors	    */
-	ldr	r2, =_armboot_start	/* r2 <- past vectors		    */
-	sub	r1,r1,r1		/* destination 0x00000000	    */
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	ldr	r2, =_armboot_start	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
 
 copy_vec:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
 	ble	copy_vec
 
-	ldmfd	r13!,{r4-r10,pc}	/* back to caller		    */
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
 
 #endif /* #ifdef CONFIG_CM_REMAP */